The following repository consists of knowledge gained and steps followed while doing the Advanced Physical Design Using OpenLANE/SKY130 workshop. The workshop focuses on the complete ASIC flow approach from RTL2GDS using open soucrce EDA tools such as OpenLANE/SKY130. RISC-V architechture is followed for designing the the core of PICORV32A.
- About RTL to GDSII Flow
- SKYWater130 PDK
- OpenLANE
- Tools Used
- AIM
- Day 1 - Inception of open-source EDA, OpenLANE and Sky130 PDK
- Day 2 - Good floorplan vs bad floorplan and introduction to library cells
- Day 3 - Design library cell using Magic Layout and ngspice characterization
- DAY 4 Pre-layout timing analysis and importance of good clock tree
RTL (Register tranfer level) to GDSII (Graphic Data Stream) flow consists of the complete set of steps required to create a file which could be sent for tapeout. The RTL code is synthesized and optimised. After sysnthesis of the code, PnR, floor and power planning is done while keeping in check the timing constraints. At the end GDSII file is written out. The complete flow consists of following steps:
- Writting RTL
- Synthesis
- STA (Static Timing Analysis)
- DFT (Design for Testability)
- Floorplanning
- Placement
- CTS (Clock Tree Synthesis)
- Routing
- GDSII Streaming
It is a Open source PDK (Process Design Kit) which is released by the collabration of Google and SkyWater Technologies foundary. Currently this technology has a target node of 130 nm. It is open to everyone and can be accessed at SkyWater Open Source PDK. This PDK is extremely flexible as it provides many optional featurs as standard features. Hence it povide designers with wide range of design choice.
It is an open-source VLSI flow created using open source tools. Basically it is collection of various scripts which invoke and execute these tools in right sequence, modifies inputs and outputs and gives an organised results.
| Tool | Used for |
|---|---|
| Yosys | Synthesis of RTL Design |
| ABC | Mapping of Netlist |
| OpenSTA | Static Timing Analysis |
| OpenROAD | Floorplanning, Placement, CTS, Optimization, Routing |
| TritonRoute | Detailed Routing |
| Magic VLSI | Layout Tool |
| NGSPICE | SPICE Extraction and Simulation |
| SPEF_EXTRACTOR | Generation of SPEF file from DEF file |
In the complete flow to this RTL2GDS physical designing there are lot of terminologies one comes across. Some of these terms are described below.
- Package - ICs are basically presents as packages. These packages are materials which contains the semiconductor device. These packages protect the device from damage. these are of various kind. An example of QFN-48 (Quad Falt No-Leads) with 48 pins is taken here.
- Chip - It sits in the centre of the package. The chip is connected to the package pins using wire bond. Inside the chip we have various components such as pad, core, interconnects, etc.
- Pads - These are the itermediate structure through which the internal signals from the core of IC is connected to the external pins of the chip. These pads are organised as Pad Frame. There are different kind of pads for input, output, power supply and ground.
- Core - It is the place where all the logic units (gates, muxs, etc) are presnet inside the chip. These are able to execute the set of instructions given to the chip and produce an output.
- Die - It is the block which consists of semiconducting material and it can be used to build certain functional cuircuit which can be further sent for fabrication. It is the entire size of the chip.
RISC-V is an open instruction set architechture rooted on reduced instruction set computer principles. It is an open source ISA used for processor design.
- It uses one clock cycle per instruction.
- It follows the th RISC Princples.
- It has both 32-bit and 64-bit varients. It also support floating point instruction.
- It avoids micro-architechture or technology dependent features.
- It accelerates the time for design to reach the market as it uses open-source IP.
The flow shows how the high level language (at software end) gets converted to machine language (at hardware end) and then gets executed on the package.
Suppose a C program needs to run on a hardware. So we nned to pass this C program to the hardware. So firstly the C program is compiled into assembly language (RISC-V assembly language program). Now this assmebly language is converted into the machine language program (basically 1's and 0's). Now this 1's and 0's are understanable by the hardware.
- The application software enters the system software (major component of it are OS, Compiler and Assembler).
- The OS handles I/O operations, memories and many low level functions.
- then the program passes to Compiler which changes the program to Assembly language (compiled into instructions depends upon the hardware).
- Now the instruction set goes to Assembler. Assembler converts the instruction set to machine language (binary numbers).
- The system software converts the apllication software into binary language.
- Now these binary numbers enter our chip layout and according the function is performed.
For designing Digital ASIC ICs we require following components and some of it's opensource resources are also mentioned.
- RTL models (old IP's) {github.com, librecores.org, etc}
- EDA tool {OpenROAD, OpenLANE, etc}
- PDK Data {SKYWater 130}
In the workshop every component is used from sources which are open soucre. The following image gives an idea about each component as an open source resource.
PDK stands for Process Design Kit, it is provided by foundaries and it consists of library or set of building blocks which are used to build ICs. Each component in the library is seperate building bolck and ae made following certain foundary rules.
PDKs acts as an inteface between the FABs and the designeers. PDKs have collection of files whcih are used to model a fabrication process for the EDA tools used to design an IC. PDK consists of tecnology node information, Process Design Rules (to verify DRC, LVC, PEX, etc), device model, I/O libraries, Standard cell libraries, macros files, lef files, etc.
Google along with SKYWater made the laters PDK opensource (130 nm node). The PDK only need data information for successful implementation.
The OpenLANE flow requires various open source tools as well as their supporting tools to be installed for the complete Physical design flow. Installing this tools one by one is tedious as well as one can get lost in the steps. Installation can be done easily using some set of scripts present in following repositories VSDFlow (for installing Yosys, OpenSTA, Magic, OpenTimer, netgent, etc) and OpenLANE Build Scripts.
The flow starts from the HDL code i.e.RTL model and ends with GDSII file. The major implimenation steps are:
- Synthesis - During synthesis the HDL design is translated into circuits, which are made up of components present in the standard cell library. The resultant circuit is described in HDL and its referred as gate level netlist which is functional equivalent of RTL code. The library building block of cell have regular layouts, cell layout is enclosed by fixed height (rectanglar in shape) whereas the width is variable an is discrete i.e., integer multiple of unit call side width.
- Floor Planning - In Floor planning the chip area is being planned which in turn creates a robust Power distribution to power the circuits. The die is partitioned into different building blocks or components, also the I?O pads are distributed. During macro floor planning macro dimensions, it's pin locations and row definations i.e, rows and routing plan.
- Power Planning - The power network is constructed typically for a chip was it has to power multiple VDD and ground pins. The power pin are connected to all component through rings and multiple horizontal and vertical strips. Sach parallel structure is meant to reduce the resistance.
- Placements - For macros we place the GATE level netlist cell on vertical rows. To reduce the interconnect delay conical cells are placed very close to each other and this is also done to enable successful routing afterwards. Placement is done in two ways Global placement and detailed placement. Global placement provide optimal result and these may or may not be legal where as the detail placement is always legal.
- Clock Tree Synthesis (CTS) - Before signal routing clock routing is done so that the clock distribution is done to every sequential block. Clock distribution network delivers the clock to each of the sequential block. It is done so that there is minimum skew and latency. It usually follows a shape i.e., H-tree, X-tree, etc.
- Routing - The signal routing is done using metal layers. It is essential to find valid pattern of horizontal and verticle wires to implement the nets that connects the cells together. Router uses the available metal layers as defined by the PDK. For each metal layer the PDK defines the thickness, width, pitch and vias. Vias are used to connect two metal wires. SkyWater 130nm has 6 metal layers.
- Verification and Sign-offs - After PnR and CTS we perform verifications, to check whether our layout is valid or not. These verifications consists of Physical verification such as DRC and LVS. Design Rules Checking (DRC) ensures that the layout follows the design rules and Layout Vs Schematic ensures that the final layout is as per the synthesised gate level netlist or not. Finally Static Timing Analysis is done (STA) to make sure that all the timing constraints are met by the circuit.
OpenLANE is a flow which uses various open source tools for the RTL to GDSII flow. It has the striVe family of open everything SoCs (Open PDK, Open EDA, Open RTL). The various tools it uses are Yosys, OpenROAD, Magic, Netgen, SPEF_Extraction, etc.
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It has two mode of Operations: Autonomus and Interactive
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It is tuned for SKYWater 130nm open PDK.
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OpenLANE ASIC flow is shown below.
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The flow starts with RTL Synthesis. RTL is fed to Yosys with the design constraints. Yosys translates the RTL into a logic circuit using generic components.
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the circuit can be optimized and then mapped with standard cell library usin the tool abc. There are abc scrript to guide the optimization. OpenLANE has several abc scripts which has different synthesis statergies (least area, least power consumption, etc). The synthesis exploration utility is for statergy exploration and report generation.
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OpenLANE has design exploration utility which can be used to sweep the design configurations (16 in total) and it genrates reports which has different design matrix and also shows the number of violations in layout. It is used for regression testing and to find the best configuration of our design.
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OpenSTA performs the Static timing analysis on the netlist which is generated during synthesis.
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Now after synthesis, the testing part starts (DFT) i.e., scan insertion, Automatic Test Pattern Generation (ATPG), Test Pattern Compaction, Fault Coverage and Fault Simulation. This step is optional.
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Nest step is Physical implementation. This part is done with the help of OpenROAD application. It performs PnR which consists of FP+PP, Placement (Global and Detailed), Optimization, CTS and routing (Global and Detailed). TritonRoute is used for detailed routing.
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Logic equivalence checking (LEC) is performed as the circuit changes due to optimization process as compare to the one generated during synthesis. This is done using Yosys tool to make sure the functionality is equivalent.
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During insertion there is a special step that is fake antenna insertion. It is required to address the antenna rule violations. The concept of fake antenna is something like we have already considered the antenna so that on later stage we do not have any antenna violations. Hence we add fake antenna diode next to every cell input after placement. Then antenna checker is run from the Magic tool against the layout.
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Fake antenna diode cell is created and added to standard cell library.
/hence a long wire is simulated it acts as an antenna but as a conductor it collects charges which can damage the transistor gates connected to the wire during fab. So the length of wire connected to transistor gate must be limited. This is done by the help of Router./
- The sign off include STA, DRC and LVS. It also involves interconnect RC extraxtion from the routed layout followed by STA using OpenSTA.
- Physical signoffs include DRC and LVS. DRC and LVS is performed using Magic tool. Circuit extraction is done NetGen.
The following content is specific to the workshop. There are lot of other files present in the directory too.
- OpenLane folder - It contains all the tools and the file that need to be invoked during the flow.
- Designs - This folder consists of all the designs requried during the flow (picorv32a is the design used in this workshop)
- PDKs - This folder contains all the pdk related files as well as information. (open pdk, Sky130, Skywater pdk).
- open pdk consists of the scripts.
- sky130A pdk consists of the libs.ref (has files specific to process such as timing, lef-both tech and cell) and libs.tech (has all the files specific to the tool) files.
- skywater pdk consists of skywater 130 nm pdks.
NOTE: - Here sky130_fd_sc_hd libs.tech is being used. 4. config files - It bypasses any configuration that has already been done i.e., many of the switches use default value that is already present in the OpenLane flow. The precedence order of Openlane settings are:
- sky130_xyz_config.tcl
- config.tcl
- Default value (already set in OpenLane)
Step 1: Starting OpenLane
- Go to openlane folder.
cd work/tools/openlane_working_dir/openlane
- Then run the docker command.
docker
- Now run the flow.tcl file with interactive mode.
./flow.tcl -interactive
- Now import packages
package require openlane 0.9
- Now we are good to go to execute our commands.
NOTE - The above commands are to be run everytime we use OpenLANE for RTL2GDSII flow.
Step 2: Design Preperation
- Knowing the contents of our design (picorv32a) folder.
- src
- sky130A_sky130_fd_sc_ns_config.tcl
- sky130A_sky130_fd_sc_ls_config.tcl
- sky130A_sky130_fd_sc_hs_config.tcl
- sky130A_sky130_fd_sc_hdl_config.tcl
- sky130A_sky130_fd_sc_hd_config.tcl
- config.tcl
Checking our config.tcl file values by running the below command in picorv32a folder (it has clock period of 5 unit)
less config.tcl
- Creating file for our design i.e., setting up the design. It merges the cell LEF files and the technology LEF files generating merged.lef which is present in the temp folder.
prep -design picorv32a
This marks the creation of new folder inside picorv32a named as runs folder which consists of new folder whose name is the date on which the command is run. The following folder has results, reports, command logs, PDK Sources, etc files.
Step 3: Running Synthesis
Yosys synthesis is run when the command for synthesis is entered. Along with it abc scripts are also run and OpenSTA is also run.
run_synthesis
After running systhesis logs, reports and results are created.
The report folder have the following files:
- 1-yosys_4.chk.rpt
- 1-yosys_4.stat.rpt
- 1-yosys_dff.stat
- 1-yosys_pre.stat
- 2-opensta.min_max.rpt
- 2-opensta.rpt
- 2-opensta.slew.rpt
- 2-opensta.timing.rpt
- 2-opensta_tns.rpt
- 2-opensta_wns.rpt
Also a netlis file is created in the results --> symthesis folder named picorv32a.synthesis.v
Count of d flip flop (sky130_fd_sc_hd_dfxtp_2) = 1613
Number of cells = 14876
flop ratio = count of d flip flops / number of cells = 1613/14876 = 0.108429 (10.8429 %)
The synthesis statisttics report is as follows:
Here we try to come up with the width and height of the chip.
- Determining width and height of the core and die While defining the dimensions of the chip we are mostly dependent on the dimensions of the logic gates (standard cells) sitting in the netlist.
- Core is the section where fundamental logic is being place whereas a die is a small semiconductor material specimen on which the fundamental circuit is fabricated and it consists of core.
- Once the logic is placed in the core it utilizes certain amount of core which is characterised by utilization factor (Area occupied by netlist / total area of the core). If utilization factor = 1 it means 100% utilization, hence no extra cells could be added. Therefore in a practical scenario the core utilization factor is always less than 1. Hence we generally go for 50-60% utilization. utilization factor = 0.5-0.6)
- Another important consideration is aspec ratio ((height)/(width) of the core). If aspect ratio = 1 it means the chip is square in nature.
Generally the utilization factor is less than 1, hence we have some un used section of core. These unused section of the core is used for optimization and other things. In the unused section we place additional cells, used for routing, etc.
Pre-placed cells - It is based on the concept of reusable modules or IP's. These blocks need not be implemented everytime we need to use it, these blocks are functionally implemented sometime in the past i.e., only once (for eg - memory, clock-gating, vomparator, mux,etc). These cells are called pre-placed ceels. It's needed to define the placement of these cells or IP's in a chip before routing. These have fixed places on the chip defined by the user. Since these cells are placed before placement and routing hence these are called Pre-placed cells. The pre-placed cells are being placed on a core depending on the design scenario. Automated placement and routing tools does not touch these cell positions.
The pre-placed cells needs to be surrounded by De-coupling capacitors. Whenever there is a switching in a circuit there is amount of current required because basically there is small capacitor present at each node, so (switching from 0 to 1) means the capacitor has to charge to represent logic 1 and the amount of charge is sent from the supply voltage. So, it is responsiblity of the supply voltage to supply the amount of current to the switching logic. Also while 1 to 0 switching it is the responsibility of VSS to take all the charge hence thre is discharge current. Now due to wire resistance, inductance there is a drop in the voltage across the wire during flow of current. There is a drop because these wires are vias hence it has physical dimensions hence it has res, cap, inductance etc. Now due to the drop there is VDD' at the node i.e., instead of 1V (VDD) we have 0.7V (VDD') The 0.7 V (VDD') should be in our noise margin range. So, if the VDD` lies in the noise margin range then we are safe but sometimes we can be unsafe. To ensure the safety we use decoupling caps, these are huge caps filled with charge and the equivalent voltage across the caps are same as supply voltage. Hence the required current is provided by this caps. This caps de-couples the circuit from the main supply whenever there is switching. Now we have taken care of local communication. Next we need to focus on global communication.
There a lot of macros on a chip and if each macro has it's current demand so there will be lot of de-coupling capacitor which is not feasible. Therefore, some critical blocks are decoupled using de-coupling cap but not for each element. There is always a posibility of voltage drop at certain node in the circuit. Suppose there is a 16 caps connected in parallel and all are going to switch from logic 1 to logic 0 i.e., caps are discharging and all this connected to same ground. All of these caps discharge at same time then there is a ground bounce (bump at the ground) and if the size of the bump exceeds the noise margin then it might enter into undefined state. Also when all the caps try to charge from 0 to 1 then there is a voltage droop (demanding of power at the same time) and again the noise margin concept applies here too. This problem happens only because there is power supply at one point, if there is power supply present in the entire perpherry then this problem is resolved. Hence solution to above problem is multiple power supply and ground. Therefore we have multiple VDD and VSS ports.
The connectivity information betweer the gates is codded using VHDL/Verilog language and is called as the netlist.
There are pre-placed cells already present in the core. The area between the core and die are filled with the input and output ports. The I/O ports placement depends upon the cells connected to these ports as well as the pre-place cells. The clock ports are bigger in size as these are continously driven pins and these drives the complete chip. So we need the least resistance path for the clocks hence clock pins are thickers.
After pin placement it should be made sure that the remaining empty area between the core and the die is blocked. Therefore logical cell placement bloackage is done. Hence it ensures that automated placement and routing does not place anything in this area.
Voila!! we are done with Floor and Power Planning.
NOTE: Standard cell placement happens in placement stage.
- Netlist binding and initial place design
- Lets suppose the shape of the gate determine the functionality of the gate but in reality each gate is a black box. Hence we take each gate and give them a physical dimensions. This is done for each of the component of the netlist. These cells are present in a library which consists the following information and files shape and size, delays, various flavour of the cells and the timing information. Library akso orvide options with different delay and sizes. Particular cell is chosen as per our requirement.
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Next step is to take the particular shap and sizes and then place it on the floorplan. The pre-placed cells are not disturbed. During placement logical connectivity is maintained as well as the placement is done in such a way that optimized path is formed (i.e., blocks placed close to there input and output)
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Till now we have kept o/p port near the output and input port near the input. Now using some estimations we will try to do optimized placement. We can try to estimate the capacitances and resistance b/w two point. The wirelength will form a resistanace which will cause unnecessary voltage drop and a capacitance which will cause a slew rate that might not be permissible for fast current switching of logic gates. Successfully transmitting the signal from one place to another without any loss is known as signal eintegrity. To maintain the signal integrity we require repeaters (kind of buffers) and these are inserted as per the wire length and capacitance and based on these cap and resistance, a waveform is genrated and the transition of the waveform should be in permisible range. But now we have loss of area. Hence where integrity is maintained there we do not place any repeaters but if integrity not maintained the we insert the buffer (repeater). We need to come to a conclusion with minimum number of repeater. Sometime we also do abutment where logic cells are placed very close to each other (almost zero delay) if it has to run at high frequency (2GHz). Crisscrossing of routes is a normal for PnR and it can be avoided by use separate metal layer (using vias) for crisscrossed path.
Based on ideal condition of the clock (time required by clock to reach a component is 0) we will do setup timing analysis and based on this we will check our placement condition is meeting the given specification or not.
Placement in OpenLANE is done in two stages:
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Global Placement - It's main job is to reduce the wire length. It is generally a coarse placement. Here no leaglization happens. Here the concept of HPWL (Half Parameter Wirelength) reduction model.
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Detailed Placement - legalization happens here the std. cells are placed in std cell rows. {legalization - They shoulde be exactly inside the row and the should be abutted on each other and there should be no overlap}.
The main ain of placement now is congestion, it is not the timing analysis. The next step will be CTS.
Placement before buffer insertion:
Placement with buffers
Our objective is to converge the value of Overflow (it is present below HPWL value during run_placement. If the value of overflow decreases our design will converge. Now we can see the generayed .def file in the placement folder under results using the Magic tool.
**NOTE: ** Collection of gates in an area is called as library.
In IC design flow a library is a place where we keep all our standard cells, buffers, decap cell, etc. The library does not only have different cells with different functionality but it also have same cell with different sizes, threshold voltage, delays, etc.
- Examining an inverter
Cell design flow is divided into three parts: inputs,design steps and outputs.
- Inputs - Inputs to design an inverter is basically the PDKs which consists of DRC & LVS rules, SPICE models, library and user-defined specs.
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DRC & LVS Rules - These are the technology rules defined by the foundary. tech files and poly subtrate paramters (CUSTOME LAYOUT COURSE)
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SPICE Models - These consists of all the parameters based on the foundary for eg: Threshold voltage, linear regions, saturation region equations with added foundry parameters. Including NMOS and PMOS parameteres (Ciruit Deisgn and Spice simulation Course)
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User defined Spec = These are the specifications given by the user which is to be achieved by following the DRC and LVS rules. Maintaining Cell height (separation between power and ground rail), Cell width (depends on drive strength), supply voltage(provided by top level, keep noise margin in check), metal layer requirement (which metal layer the cell needs to work), pin location, drawn gate length, etc.
Now we have all the inputs with us (available with the library developers). Now the developer should take the input and come up with std cells that adheres to these specs and rules.
- Design steps - It has three different steps:
circuit design,layout designandcharacterisation.
- circuit design includes the implentation of the logic and the modeling W/l ratio of NMOS and PMOS.
- Implementation of the circuit description language (i.e., output of the circuit design) is called layout design.
Steps in layout design:
1. Get the function implemented using CMOS.
2. Get a PMOS and NMOS network graph out of the implemented circuit. (using Euler's method)
3. Obtain the Euler's path, it is a path that is traced only once.
4. Draw the stick diagram.
5. Convert the stick diagram into layout adhering with the DRC rules given by the foundary.
The layout is generated using Magic tool .Now we have the cell width and cell height and all the cells adhere to the rules.
We can extract the parasitics from the layout and we have characterise it with respect to timing.
- Outputs - The output of the layout desgn is GDSII. Lef defines the width and height of the cells. It also gives extracted spice netlist.
Now we will do chararacterisation and we will generate timing, noise, power libs function. Here we will try to understande various syntax and symantic of timing.lib, power.lib and noise.lib. These syntax are important to understand the GUNA software i.e., the characterisation software because software works on these variables and these are the variables present with us in order to feed into the software.
- Timing charaterisation
Here we first understand different threshold point of waveform itself called as timing threshold defination.
Consider the above two inverter figure and understand the graph below. red curve - input to the circuit at 2nd inverter, blue curve - output of the circuit after 2nd inverter. We have slew deniation shown in the figure below for both rising and falling edge. With help of all the timing threshold defination we are able to calculate our slew as well as the propagation delay.
Similarly we have threshold for the delays (rise and fall) as we had for slew hence we analyse the waveform for the delays.
Getting a negative propagation delay is highly unexpected. A negative propagation delay means that the output comes before the input. Hence to avoid negative propagation delay we as designer need to choose correct threshold points which eventually leads to positive delays. Propagation delay threshold is usually 50% and slew rate threshold is 20-80%.
Continuation after synthesis.
Step 1: Running floorplan
- We have lot of switches with which we adjust the flow directory. These switches are used to set certain parameter in each stage of the flow. For eg: In the Floorplanning stage we have
FP_CORE_UTIL {for utilization percentage},FP_ASPECT_RATIO {sets the aspect ratio},FP_CORE_MARGINS {offset b/w die boundary and core boundary}, etc. We have certain .tcl file in OpenLane which has these switchs that sets these specifications.
├── README.md
├── checkers.tcl
├── cts.tcl
├── floorplan.tcl
├── general.tcl
├── lvs.tcl
├── placement.tcl
├── routing.tcl
└── synthesis.tcl
floorplan.tcl contains the following default switchs
- The command to run floorplan is:
run_floorplan
Step 2: Review floorplan files and steps to view floorplan
- Reviewing files
Here basically the ceated files are being checkd using the log files presen in the log/floorpla/4-ioPlacer.log. In case it is not there we can check it using the Magic tool.
- for floorplan the core utilization is 50%
- for config.tcl file under the runs folder core utilization is 35%.
- setting the core utilization, verticle and horizontal metal layer by add these three switchs in the config.tcl file
set ::env(FP_CORE_UTIL) 65
set ::env(FP_IO_VMETAL) 4
set ::env(FP_IO_HMETAL) 3
- Viewing Floorplan
The def (design exchange format) file is created in the floorplan folder of the results folder under runs folder. This file has the information about the die area. This gives the co-ordinates of the die and the unit is databse unit per micron i.e. 1 micron = 1000 database units)
The die co-ordinates and other information can be viewed using following command invoked under the picorv32a folder.
cd runs/[date]/results/floorplan/picorv32a.floorplan.def
NOTE: 1 micron is equivalent to 1000 database units
Calculating the die area = (660685 / 1000) x (671405/1000) = 443587.2124 um 2
Step 3: Review floorplan layout in Magic
- Using Magic tool to view the def file
The following command can be used to invoke magic tool as well as open the def file:
magic -T /home/nickson/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &f
To center the view, press "s" to select whole die then press "v" to center the view. Point the cursor to a cell then press "s" to select it, zoom into it by pressing 'z". Type "what" in tkcon to display information of selected object. These objects might be IO pin, decap cell, or well taps as shown below.
The genrated file is shown below:
The horizontal and verticle pins:
The decap cells:
The diagonally equidistant tapcells:
The standard cells in the bottom left corner:
Step 4: Running Placement
The following command is used to run placement.
run_placement
During place a number of tools such as RePlace tool (for global placement), Resier tool (for optimization) and OpenDP (for detailed placement) is invoked. If the value of overflow converges then the design is legal.
- Using Magic tool to see the layout of this stage.
magic -T /home/nickson/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
The genrated layout:
Placement ensures that the standard cells are correctly placed. PDN is created during floorplan. But is Openlane there is a post floorplan, post placement and CTS is done for PDN.
Here we will be dive deep into the flow. We will take a .mag file and do post-layout simulation in ngspice. After post-characterising we will be plugging this cell into the openlane flow i.e., into picorv32a core.
- IO Placer revision Earlier we had equidistant placed input/output pins. Now lets say we want to change it to some othe input/output pin statergy (there are four statergies supported by IO Placer - the tool that we use for IO placement). So we can change the switch (variable) and this will change the statergy and this can be done directly by setting the variable through the terminal and then re-run the floorplan.
EXAMPLE - changing PIN configuration
set ::env(FP_IO_MODE) 2;
run_floorplan
Then check the layout by launching Magic again.
- SPICE deck creation for CMOS inverter
Here we will do SPICE simulation and deriving the charactestic on real time MOSFETs.
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SPICE Deck - It is a connectivity information about a cell. It is a netlist. It has the inputs, tap points, etc.
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We need to define the component parameter i.e., value for PMS and NMOS. For us value of W/L of PMOS M1 (0.375u/o.25u) and NMOS M2 (0.375u/0.25). Ideally PMOS should be 2 or 3 times wider than NMOS. The load cap is assumed to be 10 fF.
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We assume an input supply voltage value (GATE) as 2.5 V and main supply voltage (at drain) as 2.5 V. Generally the supply voltage (GATE) is multiple of length.
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Now we need to identify the node (those two point in b/w there is a component) and name these nodes.
The SPICE Deck is written below:
*** MODEL Description ***
*** NETLIST Description ***
M1 out in vdd vdd pmos W=o.375 L=0.25 *** [component name] [connectivity] [drain] [gate] [source] [substrate] [type] [dimensions W/L] ***
*** Similarly for NMOS ***
M2 out in vdd vdd nmos W=o.375 L=0.25
*** load cap connecivity and value [name] [node1] [node2] [value] ***
cload out 0 10f
*** Supply voltage [name] [node1] [node2] [value] ***
Vdd vdd 0 2.5
*** Input voltage [name] [node1] [node2] [value] ***
Vin in 0 2.5
*** Simulation Command ***
.op
.dc Vin 0 2.5 0.05 *** Sweeping gate input form 0 to 2.5 at steeps of 0.05 VTC curve***
*** describe the model file ***
.LIB "tsmc_025ummodel.mod" CMOS_MODELS
.end
First invoke the ngspice and then run the following command to simulate:
source [filename].cir
run
setplot
dc1
plot out vs in
- Vm (switching threshold voltage) - The point where exact transition takes place i.e., Vin = Vout. At this point both the MOS are in saturation and we have a high leakage current (direct current flowing from vdd to ground). If the pull up network is strong the VTC moves towards right (Vm' > Vm) and if pull down network is strong then VTC shifts leftwards (Vm' < Vm).
Formula for Vm
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Propagation delay - The difference between the time when output as well as input is at 50%. ( o/p falls and i/p rises gives fall delay, o/p rises and i/p falls gives us the rise delay)
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We can furter do transient analysis.
- We will first git clone one of the repo (it is custom made for the workshop). Here we have .mag file for INVERTER, model file for sky130nm PMOS and NMOS. We will creat a ful view cell and then we will plug it into our flow.
The command for git clone is (run it while you are in the openlane directory):
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
It will create vsdstdcelldesign design folder.
We need to have the tech file to open the mag file. We will copy the tech file to our directory. the tech file is present in the sky130A which is inside pdks folder.
The tech file is present at this location work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic.
cd work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/
To copy go to the location and then type the command given below with target location
cp sky130A.tech /[target location]
target location for our case - /home/ee22mtech14005/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign
Now invoke magic tool in the vsdstdcelldesign folder to see the mag file i.e., layout of the inverter.
Command
magic -T [tech file] [.mag file]
tech file = sky130A.tech .mag file = sky130_inv.mag
The generated layout:
- Selecting a substrate
- Creating active region for transistor
- N-Well and P-Well Fabrication
- Formation of Gate
- Lightly Doped Drain formation
- Source and Drain Formation
- Form Contacts and Interconnects
- Higher Level Metal Formation
Step 1 : Characterisation
We try to analyse the layout part by part using the what command in tkcon window.
lef (library exchange format) - it has all the information about metal layers. It also protect the IP.
def (design exchange format)
To implement the complete CMOS inverter click here.
Magic is interactive DRC tool. If we have DRC it will show automatically. For our design we do not have any DRC violation. We need to ensure that our final design in DRC clean.
To know the logical function of the inverter we first extract the SPICE. Post that we will do simulation the file using ngspice.
To extract it on SPICE, type these command in the tkcon window:
- create an .ext file -
extract all(extracted in vsdstdcelldesign folder) - We will use this ext file to buide our SPICE file which can be used with the ngspice tool. Doing this will extract all the parasitics too.
ext2spice cthresh 0 rthresh 0
ext2spice
- seeing whats inside the spice file.
vim sky130_inv.spice
So our stand cell and extracted SPICE model is now present with us.
The above SPICE model give connectivity information of our inverter. Now for transient analysis we have to define the connections.
- We want VGND to be connected to VSS
- We want supply voltage (VDD) to be connected form VPWR to VSS (ground).
- So we create a node 0 and give VDD = 3V.
- Then we give pulse voltage between A and VGND (VSS).
We need to ensure that scaling is proper. (set to grid value specified in the layout). We can check the dimension of a grid in layout by the command box.
Add these command to our SPICE DECK
.option scale = 0.1u //set scale to 0.01 u.
.include ./libs/pshort.lib
.include ./libs/nshort.lib
// comment out the .subckt line
// change name of model from pmos (sky130_fd_pr__pfet_01v8) to pshort_model and from nmos(sky130_fd_pr__nfet_01v8) to nshort_model
VDD VPWR 0 3.3V //supply
VSS VGND 0 0V //ground
Va A VGND PULSE (0V 3.3V 0ns 0.1ns 0.1ns 2ns 4ns)
// comment .end
//transient
.tran 1n 20n
.control
run
.endc
.end
error
It gave us error that subckt hence I referred to the following link for exact SPICE file here.
* SPICE3 file created from sky130_inv.ext - technology: sky130A
.option scale=0.01u
.include ./libs/pshort.lib
.include ./libs/nshort.lib
* .subckt sky130_inv A Y VPWR VGND
M0 Y A VGND VGND nshort_model.0 ad=1435 pd=152 as=1365 ps=148 w=35 l=23
M1 Y A VPWR VPWR pshort_model.0 ad=1443 pd=152 as=1517 ps=156 w=37 l=23
C0 A VPWR 0.08fF
C1 Y VPWR 0.08fF
C2 A Y 0.02fF
C3 Y VGND 2fF
C4 VPWR VGND 0.74fF
* .ends
* Power supply
VDD VPWR 0 3.3V
VSS VGND 0 0V
* Input Signal
Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)
* Simulation Control
.tran 1n 20n
.control
run
.endc
.end
After editing we launch the ngspice to see the values:
command
ngspic [spice file] // our case sky130_inv.spice
We can now see the plots (inside ngspice type the command below:
plot y vs time a
The transient plot is shown below:
Characterisation involves four parameters:
- rise transiton - time taken by output waveform to transit from 20% to 80% of VDD 20% value (0.66) = 2.1829 ns
80% value (2.64) = 2.24407 ns
Hence rise time = 2.24407 - 2.1829 = 0.06117 ns
- fall transition - time taken by output waveform to transit from 80% (2.64) to 20% (0.66) of VDD.
fall time = 0.02725 ns
3 & 4. Propagation delay - The difference between the time when output as well as input is at 50% (1.65). ( o/p falls and i/p rises gives fall delay, o/p rises and i/p falls gives us the rise delay)
- fall delay:
output falling (50%)
input rising (50%)
Therefore delay = 8.07761 - 8.05075 = 0.02686 ns
- rise delay:
output rising (50%)
input falling (50%)
Therefore delay = 6.15075 - 6.15 = 0.00075 ns
The above characterisation is done at 27 C.
Next objective is to use this layout of inverter to create a lef file. Using this lef in openlane and plugging this cell we will make a custom cell. We will plug this in picorv32a.
Step 2: DRC rules analysis
To know more about Magic and the command for DRC visit the following link. Technology files have all the technology related file. It consists all information about the layer, pattern, electrical connectivity, GDS generation rule, DRC rule, all other kind of rules, etc. Tnformation about the technology files can be found here.
NOTE: cif - caltech intermediate formate - It is used interchangably with gds in magic tech file and documentation. Read through the website for DRC rules. The basic DRC rules are called edge based rules.
- We will download the required DRC_test files using the command.
wget http://opencircuitdesign.com/open_pdks/archive/drc_test.tgz
Upon extraction we find that there are .mag files and sky130A.tech file.
Now we can use magic to analyse the DRC rule and fix it if it's violated.
OpenLANE is a Place and Route flow and for placement of any cell we do not require the entire mag file information. .mag file has all the information the power, ground, logic, metal, etc. For PnR do not require all the information. Only info we need is the PR boundary, power rail, ground rail, input and output. Here lef files come into picture. lef files has only these information. It protects our IP.
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Now our objective is to extract the lef file from .mag file and then try to plug the lef file to picorv32a. (that is instead of std cell we will use our own design)
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Guidlines for std cell set making from PnR point of view.
- The input and the output port must lie on the intersection of verticle and horizontal tracks.
- Width of standard cell must be in odd multiple of track pitch and height should be off odd multiple of track verticle pitch.
Step go to the directory - pdks/sky130A/libs.tech/openlane/sky130_fe_sc_hd/ then do less tracks.info
tracks are used during routing. route can usually go above the track which are the layers. So, route are basically metal traces. PnR is automated process so we need to specify where do we want our route can go and this information is given by the tracks. Hence tracks are guide to route. Horizontal and verticle track pitches are mentioned.
We now werify the guideline using magice. Pressing g make the grid visible. We will converge the grid with track value so that we can verify that our ports are actually on the intesection or not. 4.