test: Adapt tests

SergioGasquez · Jan 13, 2025 · 601d439 · 601d439
1 parent 82b7284
commit 601d439
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Showing 4 changed files with 22 additions and 29 deletions.
diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
@@ -634,14 +634,14 @@ where
     }
 
     /// Writes bytes
-    pub fn write_bytes(&mut self, data: &[u8]) -> Result<usize, Error> {
+    pub fn write_bytes(&mut self, data: &[u8]) -> usize {
         let count = data.len();
 
         for &byte in data {
             self.write_byte(byte);
         }
 
-        Ok(count)
+        count
     }
 
     fn write_byte(&mut self, word: u8) {
@@ -810,7 +810,7 @@ where
         self.uart.info().apply_config(config)
     }
 
-    /// Read a byte from the UART
+    // Read a byte from the UART
     fn read_byte(&mut self) -> u8 {
         cfg_if::cfg_if! {
             if #[cfg(esp32s2)] {
@@ -1059,7 +1059,7 @@ where
     }
 
     /// Write bytes out over the UART
-    pub fn write_bytes(&mut self, data: &[u8]) -> Result<usize, Error> {
+    pub fn write_bytes(&mut self, data: &[u8]) -> usize {
         self.tx.write_bytes(data)
     }
 
@@ -1253,7 +1253,7 @@ where
 
     #[inline]
     fn write_str(&mut self, s: &str) -> Result<(), Self::Error> {
-        self.write_bytes(s.as_bytes())?;
+        self.write_bytes(s.as_bytes());
         Ok(())
     }
 }
@@ -1274,8 +1274,7 @@ where
 {
     #[inline]
     fn write_str(&mut self, s: &str) -> core::fmt::Result {
-        self.write_bytes(s.as_bytes())
-            .map_err(|_| core::fmt::Error)?;
+        self.write_bytes(s.as_bytes());
         Ok(())
     }
 }
@@ -1372,7 +1371,7 @@ where
     Dm: DriverMode,
 {
     fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
-        self.write_bytes(buf)
+        Ok(self.write_bytes(buf))
     }
 
     fn flush(&mut self) -> Result<(), Self::Error> {

diff --git a/hil-test/tests/uart.rs b/hil-test/tests/uart.rs
@@ -37,26 +37,25 @@ mod tests {
 
     #[test]
     fn test_send_receive(mut ctx: Context) {
-        ctx.uart.write_byte(0x42);
-        let read = ctx.uart.read_byte();
-        assert_eq!(read, 0x42);
+        let data: [u8; 1] = [0x42];
+        ctx.uart.write_bytes(&data);
+        let mut byte = [0u8; 1];
+        while ctx.uart.read_bytes(&mut byte) == 0 {}
+        assert_eq!(byte[0], 0x42);
     }
 
     #[test]
     fn test_send_receive_buffer(mut ctx: Context) {
         const BUF_SIZE: usize = 128; // UART_FIFO_SIZE
 
         let data = [13; BUF_SIZE];
-        let written = ctx.uart.write_bytes(&data).unwrap();
+        let written = ctx.uart.write_bytes(&data);
         assert_eq!(written, BUF_SIZE);
 
         let mut buffer = [0; BUF_SIZE];
-        let mut i = 0;
 
-        while i < BUF_SIZE {
-            buffer[i] = ctx.uart.read_byte();
-            i += 1;
-        }
+        while ctx.uart.read_bytes(&mut buffer) == 0 {}
+
         assert_eq!(data, buffer);
     }
 
@@ -85,10 +84,11 @@ mod tests {
                         .with_clock_source(clock_source),
                 )
                 .unwrap();
-            ctx.uart.write_byte(byte_to_write);
-            let read = ctx.uart.read_byte();
+            ctx.uart.write_bytes(&[byte_to_write]);
+            let mut byte = [0u8; 1];
+            while ctx.uart.read_bytes(&mut byte) == 0 {}
 
-            assert_eq!(read, byte_to_write);
+            assert_eq!(byte[0], byte_to_write);
             byte_to_write = !byte_to_write;
         }
     }

diff --git a/hil-test/tests/uart_regression.rs b/hil-test/tests/uart_regression.rs
@@ -29,19 +29,13 @@ mod tests {
         let mut buf = [0u8; 1];
         _ = rx.read_bytes(&mut buf);
 
-        // Start from a low level to verify that UartTx sets the level high initially,
-        // but don't enable output otherwise we actually pull down against RX's
-        // pullup resistor.
-        let mut tx = Flex::new(tx);
-        tx.set_low();
-
         // set up TX and send a byte
         let mut tx = UartTx::new(peripherals.UART0, uart::Config::default())
             .unwrap()
             .with_tx(tx);
 
         tx.flush();
-        tx.write_bytes(&[0x42]).unwrap();
+        tx.write_bytes(&[0x42]);
         while rx.read_bytes(&mut buf) == 0 {}
 
         assert_eq!(buf[0], 0x42);

diff --git a/hil-test/tests/uart_tx_rx.rs b/hil-test/tests/uart_tx_rx.rs
@@ -43,7 +43,7 @@ mod tests {
         let byte = [0x42];
 
         ctx.tx.flush();
-        ctx.tx.write_bytes(&byte).unwrap();
+        ctx.tx.write_bytes(&byte);
         let mut buf = [0u8; 1];
         while ctx.rx.read_bytes(&mut buf) == 0 {}
 
@@ -56,7 +56,7 @@ mod tests {
         let mut buf = [0u8; 3];
 
         ctx.tx.flush();
-        ctx.tx.write_bytes(&bytes).unwrap();
+        ctx.tx.write_bytes(&bytes);
 
         let mut bytes_read = 0;
         loop {