test: Adapt tests

SergioGasquez · Jan 13, 2025 · 04d6c37 · 04d6c37
1 parent 10a9695
commit 04d6c37
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Showing 3 changed files with 25 additions and 20 deletions.
diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
@@ -841,14 +841,19 @@ where
             }
         }
 
-        while self.rx_fifo_count() == 0 {}
-        // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html
-        cfg_if::cfg_if! {
-            if #[cfg(esp32)] {
-                crate::interrupt::free(|| fifo.read().rxfifo_rd_byte().bits())
-            } else {
-                fifo.read().rxfifo_rd_byte().bits()
+        if self.rx_fifo_count() > 0 {
+            // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html
+            cfg_if::cfg_if! {
+                if #[cfg(esp32)] {
+                    let byte = crate::interrupt::free(|| fifo.read().rxfifo_rd_byte().bits());
+                } else {
+                    let byte = fifo.read().rxfifo_rd_byte().bits();
+                }
             }
+
+            Some(byte)
+        } else {
+            None
         }
     }
 
@@ -896,9 +901,13 @@ where
     /// Read bytes from the RX FIFO without checking for errors.
     fn flush_buffer(&mut self, buf: &mut [u8]) -> usize {
         let mut count = 0;
-        while count < buf.len() && self.rx_fifo_count() > 0 {
-            buf[count] = self.read_byte();
-            count += 1;
+        while count < buf.len() {
+            if let Some(byte) = self.read_byte() {
+                buf[count] = byte;
+                count += 1;
+            } else {
+                break;
+            }
         }
         count
     }

diff --git a/hil-test/tests/uart.rs b/hil-test/tests/uart.rs
@@ -37,10 +37,9 @@ mod tests {
 
     #[test]
     fn test_send_receive(mut ctx: Context) {
-        let data: [u8; 1] = [0x42];
-        ctx.uart.write_bytes(&data);
+        ctx.uart.write_bytes(&[0x42]);
         let mut byte = [0u8; 1];
-        while ctx.uart.read_bytes(&mut byte) == 0 {}
+        ctx.uart.read_bytes(&mut byte).unwrap();
         assert_eq!(byte[0], 0x42);
     }
 
@@ -57,7 +56,7 @@ mod tests {
         let mut count = 0;
 
         while count != BUF_SIZE {
-            count += ctx.uart.read_bytes(&mut buffer[count..]);
+            count += ctx.uart.read_buffered_bytes(&mut buffer[count..]).unwrap();
         }
 
         assert_eq!(data, buffer);
@@ -90,7 +89,7 @@ mod tests {
                 .unwrap();
             ctx.uart.write_bytes(&[byte_to_write]);
             let mut byte = [0u8; 1];
-            while ctx.uart.read_bytes(&mut byte) == 0 {}
+            ctx.uart.read_bytes(&mut byte).unwrap();
 
             assert_eq!(byte[0], byte_to_write);
             byte_to_write = !byte_to_write;

diff --git a/hil-test/tests/uart_regression.rs b/hil-test/tests/uart_regression.rs
@@ -9,10 +9,7 @@
 #[cfg(test)]
 #[embedded_test::tests(default_timeout = 3)]
 mod tests {
-    use esp_hal::{
-        gpio::Flex,
-        uart::{self, UartRx, UartTx},
-    };
+    use esp_hal::uart::{self, UartRx, UartTx};
     use hil_test as _;
 
     #[test]
@@ -35,7 +32,7 @@ mod tests {
             .with_tx(tx);
 
         tx.flush();
-        tx.write_bytes(&[0x42]).unwrap();
+        tx.write_bytes(&[0x42]);
         rx.read_bytes(&mut buf).unwrap();
 
         assert_eq!(buf[0], 0x42);