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[Klaud Cold] Muse Spark Open MI355X: HiCache DRAM offload above conc 8 / [Klaud Cold] Muse Spark Open MI355X:并发大于 8 时启用 HiCache DRAM 卸载 - #4201
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Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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Thanks for the contribution!
中文感谢你的贡献!
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| Subproject commit ae3d6877c46f3147e3a5dafa46ee4cd89322e52f | |||
| Subproject commit 545233a0d36e7d21cf74bb01a4365475c9214003 | |||
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🔴 Every srt-slurm job, not only Muse Spark, would run on srt-slurm v2.51.1 again, undoing the v2.59.1 upgrade from #4167. The pointer goes back from ae3d687 to 545233a0. That commit is the exact v2.51.1 pin #4167 replaced, so this looks like a stale-branch merge artifact. It drops NVIDIA/srt-slurm#584, #573 and #602, and #4167 also deleted the #602 backport patch, so nothing restores that fix. Fix: reset the submodule to ae3d6877c46f3147e3a5dafa46ee4cd89322e52f so this PR only changes the recipe, config and changelog.
Why this was flagged
Commit 22b39af (#4167) moved inferencex-e2e/utils/srt-slurm from v2.51.1 (545233a0) to v2.59.1 (ae3d6877). It also deleted the #602 backport patch, and runners/srt-slurm/patches/ now holds only 573-participating-gpus.patch. This diff moves the gitlink back to 545233a0d36e7d21cf74bb01a4365475c9214003, and the PR description gives no reason. After merge, every srt-slurm launch on every cluster checks out v2.51.1. SGLang attention-DP workers sharing a node lose the per-DP-rank KV-event port reservation from NVIDIA/srt-slurm#584 and can collide on base port + DP rank again. The #602 fix is also gone, and no patch replaces it. On the base branch all of these fixes are present. The HiCache recipe change does not need this bump.
Verification: Trigger: any srt-slurm launch after merge, on every cluster, because the launchers check out the shared submodule pin. The diff changes inferencex-e2e/utils/srt-slurm from Subproject commit ae3d6877c46f3147e3a5dafa46ee4cd89322e52f to 545233a0d36e7d21cf74bb01a4365475c9214003. So this PR rolls the shared pin back to the exact v2.51.1 commit that #4167 replaced.
| description: | ||
| - "Enable SGLang HiCache CPU DRAM KV offloading above conc 8: the TP4/EP4 and TP8/EP8 conc 12 and 16 points add enable-hierarchical-cache with hicache-size 180 GB per rank and write_through (720 GB at TP4, 1.44 TB at TP8; dram-utilization 0.85), matching the GLM-5.2 MXFP4 MI355X SGLang sibling." | ||
| - "Conc 1, 4 and 8 stay GPU-resident with no KV offloading. Image, serve flags, DFlash2 draft and golden AL are unchanged." | ||
| pr-link: TBD |
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🔴 The supported merge script will fail on this PR because the new changelog entry uses pr-link: TBD, a placeholder the tooling does not accept. compare_entries only allows XXX, https://github.com/SemiAnalysisAI/InferenceX/pull/XXX or the PR's own link (validate_perf_changelog.py:147). Fix: set pr-link to https://github.com/SemiAnalysisAI/InferenceX/pull/XXX, the form CONTRIBUTING.md:206 documents, or to this PR's canonical URL. Then canonicalize_appended_links can rewrite it at merge.
Why this was flagged
The new block ends with pr-link: TBD at perf-changelog.yaml:10045. PR_LINK_PLACEHOLDERS holds only "XXX" and "https://github.com/SemiAnalysisAI/InferenceX/pull/XXX" (validate_perf_changelog.py:22-25). validate_added_pr_link raises "new PR entry must use ... or an XXX placeholder; found 'TBD'" for any other value (validate_perf_changelog.py:147-150). merge_with_reuse.py:631 calls canonicalize_changelog, then canonicalize_appended_links and compare_entries(..., pr_number) (prepare_perf_changelog_merge.py:88). It does this after it has already posted /reuse-sweep-run and merged origin/main. Nothing catches the error at merge_with_reuse.py:477-488, so the documented merge path aborts. resolve_changelog_conflict takes the same compare_entries path (prepare_perf_changelog_merge.py:146). PR CI does not catch this: validate_perf_changelog.main() only runs the planner (lines 330-336), never compare_entries, so the sweep goes green and the failure shows up only at merge time.
Verification: Trigger: the PR is merged through the supported merge script, merge_with_reuse. The diff appends a block ending in pr-link: TBD at inferencex-e2e/perf-changelog.yaml:10045. merge_with_reuse.py:631 calls canonicalize_changelog(pr, repo). The PR-time CI check in run-sweep.yml:97-117 (validate_matrix_compatible_change) does not call compare_entries, so it will not flag this.
| # Above conc 8 both layouts add a 180 GB-per-rank HiCache DRAM tier | ||
| # (720 GB at TP4, 1.44 TB at TP8). |
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🟡 nit (optional): Both new comments break the AGENTS.md comment rules. Each is an overview placed above a section and restates values already in the code. The recipe comment above the overrides at agentic.yaml:53-54 repeats hicache-size: 180 and multiplies it into totals. The rewritten master-config comment above musespark-fp4-mi355x-sglang-agentic-dflash (amd-master.yaml:1607-1608) restates the conc split and per-rank size. Fix: delete both, or replace each with one technical line on a specific value, such as why 180 GB per rank was chosen.
Why this was flagged
AGENTS.md lines 64-67 apply to every recipe and config. They forbid header comments above a recipe, override or section, and they forbid comments that restate the code. The comment added at agentic.yaml:53-54 sits above the whole override list and restates hicache-size: 180 times TP. The rewritten comment at amd-master.yaml:1607-1608 sits above the config key and describes its topology and conc split. That information is already in the search-space rows. Maintainers end up with comments that drift from the values they repeat, and the base branch does not have this duplication in the recipe.
Verification: Nothing breaks at runtime. Both comments break the repository's mandatory comment rules in AGENTS.md:60-67. In agentic.yaml:53-54 the diff adds a comment above the whole override list, not next to a value, that restates hicache-size: 180 and the conc split. The comment at amd-master.yaml:1607-1608 sits above the config key and restates the search-space split and the recipe's hicache-size.
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View unofficial run (performance): https://inferencex.semianalysis.com/inference?unofficialRun=38947852942 View unofficial run (accuracy): https://inferencex.semianalysis.com/evaluation?unofficialRun=38947852942 |
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/use 38947852942 |
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@functionstackx staged run 38947852942. This run remains available across future |
8250395 accidentally staged a stale local submodule checkout (545233a). Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Summary
Muse Spark Open MXFP4 on MI355X (SGLang + DFlash2, from #4127): add SGLang HiCache CPU DRAM KV offloading above concurrency 8.
enable-hierarchical-cache,hicache-size: 180GB per rank andhicache-write-policy: write_through, giving 720 GB at TP4 and 1.44 TB at TP8. These match the GLM-5.2 MXFP4 MI355X SGLang sibling.dram-utilization: 0.85puts the matrix DRAM budget at 1274 GB for TP4 and 2549 GB for TP8, so both tiers fit within the AgentX proportional limit of 3 TB per server.kv-offloading: none). The image, serve flags, DFlash2 draft and golden AL are unchanged.Context: the last #4127 sweep lost its TP8/EP8 c12 point to a
host_setupfailure on nodemia1-p01-g14, not to the recipe. This PR's sweep re-measures every point.AI model disclosure
PR checklist and change type
Type of Change
Checklist
full-sweep-fail-fast中文
摘要
为 MI355X 上的 Muse Spark Open MXFP4(SGLang + DFlash2,来自 #4127)在并发大于 8 时启用 SGLang HiCache CPU DRAM KV 卸载。
enable-hierarchical-cache、每 rankhicache-size: 180GB 及hicache-write-policy: write_through,TP4 合计 720 GB,TP8 合计 1.44 TB,与 GLM-5.2 MXFP4 MI355X SGLang 同类配置一致。dram-utilization: 0.85使矩阵 DRAM 预算为 TP4 1274 GB、TP8 2549 GB,两者均在 AgentX 每台服务器 3 TB 的按比例上限之内。kv-offloading: none)。镜像、启动参数、DFlash2 draft 和黄金 AL 均不变。背景:#4127 上一次 sweep 中 TP8/EP8 c12 点失败的原因是节点
mia1-p01-g14的host_setup故障,与配方无关。本 PR 的 sweep 会重新测量所有点。AI 模型使用说明
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