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bfddbcf
[AMD][MI35X] Bump Qwen3.5 MXFP4 MI355X SGLang single-node image to v0…
yichiche Aug 20, 2026
2ea2882
[AMD][MI35X] Disable shared-experts fusion on the Qwen3.5 MXFP4 MI355…
yichiche Aug 20, 2026
b2f142b
[AMD][MI35X] Bump Qwen3.5 MXFP4 MI355X single-node image to v0.5.18-2…
yichiche Aug 25, 2026
9bfe102
Merge branch 'main' into amd/qwen3.5-fp4-mi355x-sglang-v0.5.17
yichiche Aug 25, 2026
f0e164b
Merge branch 'main' into amd/qwen3.5-fp4-mi355x-sglang-v0.5.17
yichiche Aug 25, 2026
7216f88
Merge branch 'main' into amd/qwen3.5-fp4-mi355x-sglang-v0.5.17
yichiche Aug 26, 2026
89d62b7
[AMD][MI35X] Align Qwen3.5 MXFP4 MI355X SGLang arms with the cookbook…
yichiche Aug 26, 2026
7c74c34
Fix format
1am9trash Aug 26, 2026
8bbf6a4
[AMD][MI35X] Enable SGLANG_AITER_UNIFIED_DRAFT_EXTEND on the Qwen3.5 …
yichiche Aug 26, 2026
3c65144
Merge remote-tracking branch 'origin/main' into amd/qwen3.5-fp4-mi355…
yichiche Aug 26, 2026
ff0e873
[AMD][MI35X] Pin SGLANG_AITER_UNIFIED_DRAFT_EXTEND=0 on the Qwen3.5 M…
yichiche Aug 27, 2026
12e784b
Merge remote-tracking branch 'origin/main' into amd/qwen3.5-fp4-mi355…
yichiche Aug 27, 2026
a9fd902
[AMD][MI35X] Drop SGLANG_AITER_UNIFIED_DRAFT_EXTEND=0 and bump image …
yichiche Aug 27, 2026
d7b174d
Merge remote-tracking branch 'origin/main' into pr2640
yichiche Aug 27, 2026
25d5eee
Merge remote-tracking branch 'origin/main' into amd/qwen3.5-fp4-mi355…
yichiche Aug 28, 2026
0506754
[AMD][MI35X] Bump Qwen3.5 MXFP4 MI355X SGLang single-node image to v0…
yichiche Aug 28, 2026
5017d36
Merge remote-tracking branch 'origin/main' into amd/qwen3.5-fp4-mi355…
yichiche Aug 29, 2026
e054e0e
[AMD][MI35X] Bump Qwen3.5 MXFP4 MI355X SGLang single-node image to v0…
yichiche Aug 29, 2026
8b98e48
Merge branch 'main' into amd/qwen3.5-fp4-mi355x-sglang-v0.5.17
chunfangamd Aug 30, 2026
75f61a0
Anchor the MI355X changelog entry above the trailing entry to clear t…
yichiche Aug 31, 2026
52570c9
Re-anchor the MI355X changelog entry so the diff against main is addi…
yichiche Aug 31, 2026
4204903
Merge remote-tracking branch 'origin/main' into the MI355X image bump…
yichiche Aug 31, 2026
874d4bb
Merge branch 'main' into amd/qwen3.5-fp4-mi355x-sglang-v0.5.17
cquil11 Aug 31, 2026
93ee88e
Update perf-changelog.yaml
cquil11 Aug 31, 2026
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ python3 -m sglang.launch_server --model-path=$MODEL --trust-remote-code \
--disable-radix-cache \
--enable-aiter-allreduce-fusion --max-running-requests $CONC \
--page-size 16 \
--kv-cache-dtype fp8_e4m3 \
> $SERVER_LOG 2>&1 &

SERVER_PID=$!
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Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,7 @@ python3 -m sglang.launch_server --model-path=$MODEL --trust-remote-code \
--speculative-num-steps 3 \
--speculative-eagle-topk 1 \
--speculative-num-draft-tokens 4 \
--kv-cache-dtype fp8_e4m3 \
> $SERVER_LOG 2>&1 &

SERVER_PID=$!
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4 changes: 2 additions & 2 deletions configs/amd-master.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -313,7 +313,7 @@ qwen3.5-fp8-mi355x-sglang-disagg:
- "DECODE_MTP_SIZE=0"

qwen3.5-fp4-mi355x-sglang:
image: lmsysorg/sglang-rocm:v0.5.16-rocm720-mi35x-20260730
image: lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260825
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Outdated
model: amd/Qwen3.5-397B-A17B-MXFP4
model-prefix: qwen3.5
runner: mi355x
Expand Down Expand Up @@ -345,7 +345,7 @@ qwen3.5-fp4-mi355x-atom:
- { tp: 4, conc-start: 4, conc-end: 16 }

qwen3.5-fp4-mi355x-sglang-mtp:
image: lmsysorg/sglang-rocm:v0.5.16-rocm720-mi35x-20260730
image: lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260825
model: amd/Qwen3.5-397B-A17B-MXFP4
model-prefix: qwen3.5
runner: mi355x
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12 changes: 10 additions & 2 deletions perf-changelog.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -6427,7 +6427,6 @@
- "Raise dram-utilization from 0.80 to 0.95, matching the vLLM agentic lane on the same runner, and the TP>=8 hicache ratio from 2 to 3 so the CPU tier reflects the allocated budget. DSv4 HiCache takes a host/device token ratio, not bytes, so the recipe cannot apply TOTAL_CPU_DRAM_GB directly, and host capacity scales with both the ratio and device KV -- meaning it also grows with mem-fraction-static. Measured at ratio 2 / mem-fraction 0.835 the tier allocates 999 GB (124.88 GB per rank across 8 ranks), a third of the 2,849 GB the vLLM agentic lane consumes. ratio 4 at mem-fraction 0.93 overshot the other way, leaving 5.84 GB free on a 2,964 GB node and failing to allocate the V4 paged pool; ratio 3 keeps the tier near 2 TB with room for the paged pool, page cache, AIPerf and the router. The TP<8 ratio is left at its existing value of 8."
- "Costs TTFT (p50 2.2x, p90 3.3x); AgentX is closed-loop so this is already priced into the throughput figures"
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2701


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yichiche marked this conversation as resolved.
- config-keys:
- dsv4-fp4-gb200-dynamo-sglang
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Expand Down Expand Up @@ -6466,4 +6465,13 @@
- "Warm the aggregate low-latency profiles with the standard ten requests per trajectory lane instead of one, so they enter the profiling window from the same live state as every other AgentX recipe."
- "Reduce the concurrency-1536 disaggregated topology from six to five DEP8 prefill workers while retaining one DEP16 decode worker."
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2644


- config-keys:
- qwen3.5-fp4-mi355x-sglang
- qwen3.5-fp4-mi355x-sglang-mtp
scenario-type:
- fixed-seq-len
description:
- "Bump image from lmsysorg/sglang-rocm:v0.5.16-rocm720-mi35x-20260730 to lmsysorg/sglang-rocm:v0.5.18-rocm720-mi35x-20260825"
- "Serve both arms with an fp8_e4m3 KV cache."
pr-link: https://github.com/SemiAnalysisAI/InferenceX/pull/2640
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