[AMD][ATOM] KIMI fp4 MI355 update docker

[benenzhu]

1. Update to new ATOM images.
2. Remove Tp8, cause it consistently slower then TP4

co-author-by: Readonflow Team(@ColorsWind, @ftyghome, @jpy794) , @valarLip, @coderfeli, @Bernard-Liu

Related PRs:

1. moe:
   [PERF] MXFP4 (a4w4) MoE backend for gfx950 by ColorsWind · Pull Request #3470 · ROCm/aiter
   [RadeonFlow] MXFP4 (a4w4) MoE backend for gfx950 by coderfeli · Pull Request #3832 · ROCm/aiter
2. topk:
   perf: optimize topk kernel by ftyghome · Pull Request #3466 · ROCm/aiter
3. all_reduce:
   perf: raise fused ar 1stage limit to cover conc64 by ftyghome · Pull Request #3458 · ROCm/aiter
   [PERF] fix: Correct AR 1stage Gating Condition by ftyghome · Pull Request #3880 · ROCm/aiter
4. mla meta
   perf: add mla metadata parallel path by ftyghome · Pull Request #3465 · ROCm/aiter

Other performance-related PRs may have been missed here; please feel free to ping me to add them.

[github-actions]

Thanks for the contribution! Please reach out to respective companies' CODEOWNER to fill in the latest PR_REVIEW_CHECKLIST.md before pinging core maintainer on Slack for review. In order for the signoff PR check bot to trigger, you must follow the PR_REVIEW_CHECKLIST.md template correctly, including the phrase As a PR reviewer and CODEOWNER, I have reviewed this and have.

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[claude]

Claude finished @benenzhu's task in 3m 35s —— View job

---

Review: KIMI fp4 MI355 recipe update

• Gather context and diff against origin/main
• Review configs/amd-master.yaml changes
• Review benchmark script changes
• Validate perf-changelog.yaml entry against the changelog gate
• Post inline comments

Findings

1 blocking issue (inline comment): the new perf-changelog.yaml entry is indented 2 extra spaces ( - config-keys: instead of - config-keys: at column 0). This is invalid YAML — utils/validate_perf_changelog.py will fail to parse the file (and its append-format check would reject it anyway), so the changelog gate in run-sweep.yml fails and the sweep for kimik2.5-fp4-mi355x-atom never triggers. The suggestion in the inline comment fixes the indentation and also replaces the placeholder "TODO & update image" description with one documenting the actual changes.

1 warning (inline comment): --scheduler-delay-factor 1 was appended onto the -tp $TP line in the benchmark script; repo style requires one server-launch argument per line.

Notes

• Both issues from the previous review are resolved: the image is now the org-owned rocm/atom-dev:nightly_202607091539 (no longer a personal namespace), and a perf-changelog.yaml entry was added (correctly appended at the end).
• I could not verify externally that the rocm/atom-dev:nightly_202607091539 tag is actually published on Docker Hub (the timestamp suggests it was pushed today, 2026-07-09 15:39) — please confirm it's public before merging, otherwise the sweep will fail at image pull.
• The TP8 search-space narrowing to a single concurrency point (conc 4) for both scenarios and the new AITER/ATOM env vars look intentional; the EP flag remains correctly conditional on EP_SIZE.

Fix the changelog entry →

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29033878626
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=29033878626

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29067856301
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=29067856301

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=29068018278
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=29068018278

[benenzhu]

Recipes updated at ROCm/ATOM#1566

[chunfangamd]

/reuse-sweep-run

[chunfangamd]

As a PR reviewer and CODEOWNER, I have reviewed this and have:

• Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
• Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
• Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
• Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Range: 97.19%-97.27%; link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
• Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
• For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
• Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
• If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
• If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
• Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
  • If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
• Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/<PR_NUMBER>.md — named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section.
• If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

• insert any additional info here

Signed: @chunfangamd

[Klaud-Cold]

❌❌❌ REJECTED ❌❌❌

@chunfangamd — blocking issue: the sign-off's additional detail section is the unedited template placeholder, so the single-node recipe link is missing and the unchecked recipe checklist items have no explanation. Please post a fresh sign-off with the recipe source linked and reasoned in the additional detail section.

✅ Check 0 (CODEOWNER): PASS — @chunfangamd is a listed owner of configs/amd-master.yaml; the other changed paths carry only the catch-all.
✅ Check 1 (green sweep on in-PR commit): PASS — commit 0ed7267a (currently in this PR) has green executed single-node 1k1k/8k1k / and eval / jobs: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
✅ Check 2 (evals real): PASS — gsm8k em_strict 97.19% (conc64) / 97.27% (conc128) on amd/Kimi-K2.5-MXFP4, and the run used this PR's image rocm/atom:rocm7.2.4_ubuntu24.04_py3.12_pytorch_release_2.10.0_atom0.1.4_202607091539.
❌ Check 3 (recipe linked & complete): FAIL — no recipe link in the sign-off's additional detail section (left as "insert any additional info here") and both recipe checklist items are unchecked. ROCm/ATOM#1566 was posted in a PR comment, but it is not in the sign-off and is not one of the accepted recipe sources (vllm-project/recipes / SGLang cookbook) — the sign-off must link the recipe source and state the reasoning for this ATOM submission.
✅ Check 4 (/reuse-sweep-run posted): PASS — posted by @chunfangamd (COLLABORATOR).
❌ Check 5 (latest checklist, complete): FAIL — the template is current, but the recipe items were left unchecked with no explanation; the additional detail section is the unedited placeholder.
✅ Check 6 (upstream image / engine-first): PASS — entry is framework: atom (upstream vLLM/SGLang image rule targets vllm/sglang entries), and vLLM landed first for this model+SKU: kimik2.5-fp4-mi355x-vllm (vllm/vllm-openai-rocm:v0.24.0, mi355x).
✅ Check 7 (no architecture hacks): PASS — only precision/perf knobs (AITER_QUICK_REDUCE_QUANTIZATION=INT4, AITER_MXFP4_INTERMEDIATE=1, ATOM_DISABLE_MMAP=true, --scheduler-delay-factor 1); no model-architecture FLOPs removed, evals pass.
➖ Check 8 (spec-decode chat templates): N/A — no speculative-decoding changes in this PR.
✅ Check 9 (no engine patches): PASS — no patching of the serving stack; the diff adds env vars and a server flag only.
➖ Check 10 (agentic golden AL): N/A — no agentic speculative-decoding changes in this PR.

[chunfangamd]

As a PR reviewer and CODEOWNER, I have reviewed this and have:

• Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
• Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
• Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
• Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Range: 97.19%-97.27%; link: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
• Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
• For agentic workloads: verified that speculative-decoding configs (EAGLE / MTP / draft models) run with simulated synthetic acceptance, with the acceptance-length value taken from the committed golden AL curve in golden_al_distribution/ for that model, thinking mode, and draft length. A submission may choose any supported draft length, but it may not substitute a different acceptance target.
• Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
• If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
• If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
• Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
  • If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
• Verified that this PR does not patch the inference engine or serving stack — the pinned image must run as shipped. This covers .patch files / git apply / patch, inline patches embedded in benchmark scripts (e.g. a python3/sed heredoc that rewrites installed engine sources before serving), in-place edits of site-packages, monkey-patching, overwriting container files, and installing forked/rebuilt engine wheels on top of the pinned image. The only exception is a patch covered by a filled-out waiver at docs/waiver/<PR_NUMBER>.md — named after the PR that introduces the patch and filed in that same PR, stating what is patched, why the unmodified upstream image cannot run this benchmark, the upstream PR/issue link, and the removal plan — which I have linked below in the additional detail section.
• If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

• insert any additional info here
  [Recipe][Docs] Add MXFP4 intermediate variable and scheduler delay advice for Kimi-K2 ROCm/ATOM#1566

Signed: @chunfangamd

[Klaud-Cold]

✅✅✅ Verdict: PASS ✅✅✅

Updated verdict for this head SHA: the earlier rejection was solely about the sign-off's placeholder additional-detail section; the fresh sign-off links the recipe and checks the recipe items, and everything re-verifies green.

✅ Check 0 (CODEOWNER): PASS — @chunfangamd is a listed owner of configs/amd-master.yaml; the other changed paths carry only the catch-all.
✅ Check 1 (green sweep on in-PR commit): PASS — commit 0ed7267a (currently in this PR) has green executed single-node 1k1k/8k1k / and eval / jobs: https://github.com/SemiAnalysisAI/InferenceX/actions/runs/29068018278
✅ Check 2 (evals real): PASS — gsm8k em_strict 97.19% (conc64) / 97.27% (conc128) on amd/Kimi-K2.5-MXFP4, matching the sign-off's claimed range, and the run used this PR's image rocm/atom:rocm7.2.4_ubuntu24.04_py3.12_pytorch_release_2.10.0_atom0.1.4_202607091539.
✅ Check 3 (recipe linked & complete): PASS — the sign-off's additional detail links ROCm/ATOM#1566, which updates the ATOM engine's official upstream recipe (recipes/Kimi-K2.md) to match this PR exactly; the vLLM-recipes/SGLang-cookbook venues do not publish ATOM serve commands, so the engine's own recipe repo is the applicable public recipe source. Major args match: amd/Kimi-K2.5-MXFP4 MXFP4 on MI355, TP4 (the recipe documents MXFP4 TP4 and states different parallelism is supported), --kv_cache_dtype fp8, AITER_QUICK_REDUCE_QUANTIZATION=INT4, AITER_MXFP4_INTERMEDIATE=1, --scheduler-delay-factor 1. Informational only: ATOM_DISABLE_MMAP=true is model-load/harness tuning, and the recipe's optional --online_quant_config (ptpc_fp8 attention) is omitted here — InferenceX runs attention at higher precision than the recipe, not lower.
✅ Check 4 (/reuse-sweep-run posted): PASS — posted by @chunfangamd (COLLABORATOR).
✅ Check 5 (latest checklist, complete): PASS — matches the current template; every item is checked except the conditional "For agentic workloads" item, which is accurately left unchecked since this PR has no agentic spec-decode changes.
✅ Check 6 (upstream image / engine-first): PASS — entry is framework: atom (upstream vLLM/SGLang image rule targets vllm/sglang entries), and vLLM landed first for this model+SKU: kimik2.5-fp4-mi355x-vllm (vllm/vllm-openai-rocm:v0.24.0, mi355x).
✅ Check 7 (no architecture hacks): PASS — only precision/perf knobs (AITER_QUICK_REDUCE_QUANTIZATION=INT4, AITER_MXFP4_INTERMEDIATE=1, ATOM_DISABLE_MMAP=true, --scheduler-delay-factor 1); no model-architecture FLOPs removed, evals pass.
➖ Check 8 (spec-decode chat templates): N/A — no speculative-decoding changes in this PR.
✅ Check 9 (no engine patches): PASS — no patching of the serving stack; the diff adds env vars and a server flag only.
➖ Check 10 (agentic golden AL): N/A — no agentic speculative-decoding changes in this PR.