[SamuelReeder]

Design doc, no code: docs/hipdnn-route.md. It covers shipping the FlyDSL decode megakernels through hipDNN to vLLM via hipdnn_vllm (ROCm/rocm-libraries#14255).

• No RFC cycle. Each part lands as a small PR behind a default-OFF flag. Only two items need sign-off from another team: the hipdnn_vllm generic op and its strict-on-execute semantics (dpeabody-amd), and write access to the DVC ingestor remote (hip-kernel-provider owners).
• Fixed point and invariants H1-H7: bitwise equal, decline goes to vLLM's path, TP agreement, graph capture, co-residency, no plan or launch change by default (checked on every family wheel), no TP rank divergence after a launch failure.
• Binary key: src is vLLM's own compile_key(cfg.compiled(), kernels/), one per code object. If no width has a plan, the spec's warmup raises at startup, so host/binary drift is an error, not wrong bits.
• Geometry: vLLM's kernel copies have no rt2, so every model ships rt0 (14 objects per max_model_len) until a vLLM PR ports rt2 (step 1a). Then rt2 for Qwen3.6 and Qwen3.8 TP1; Qwen3.8 TP2 and Gemma4 (+1.81 % at M = 1) stay rt0.
• Packaging: export here, DVC ingestor remote, sha256 lock checked by the pack step.
• Risks a flag does not remove once enabled: co-residency hangs, in-place state and fallback re-run under TP2, three-repository version lock.
• Every citation is file:line at a stated commit (#14255 cb84aeb, rocm-libraries develop 2d1e830e1bb, vLLM branches, #61311 b426bf7be, megakernels main 10bd202).