Skip to content

允许重写中断控制API以支持独立的中断管理 #9305

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Rbb666 merged 2 commits into from
Aug 29, 2024
Merged

允许重写中断控制API以支持独立的中断管理 #9305

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
d9956be
[libcpu][arm][cortex-m4] allows rewrite to interrupt enable/disable a…
Evlers Aug 14, 2024
aac9c8c
add readme files
Evlers Aug 29, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions libcpu/arm/cortex-m4/context_gcc.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
* 2013-06-18 aozima add restore MSP feature.
* 2013-06-23 aozima support lazy stack optimized.
* 2018-07-24 aozima enhancement hard fault exception handler.
* 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
*/

/**
Expand All @@ -32,6 +33,7 @@
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.weak rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS r0, PRIMASK
Expand All @@ -42,6 +44,7 @@ rt_hw_interrupt_disable:
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.weak rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, r0
Expand Down Expand Up @@ -208,6 +211,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I

/* clear the BASEPRI register to disable masking priority */
MOV r0, #0x00

@Rbb666 Rbb666 Aug 29, 2024

Copy link
Copy Markdown
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

我看已经实现了虚定义，原来的这块为什么还要改呢？

@Evlers Evlers Aug 29, 2024

Copy link
Copy Markdown
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

  • 因为在rtthread_startup函数中调用了rt_hw_interrupt_disable函数来屏蔽中断，但是之后没有再调用rt_hw_interrupt_enable函数来禁用屏蔽中断，而是直接在rt_system_scheduler_start函数中调用rt_hw_context_switch_to来启用中断。
  • 而rt_hw_context_switch_to中使用CPSIE指令来启用中断，所以需要在CPSIE之后清除basepri寄存器以禁用中断优先级的屏蔽。

MSR BASEPRI, r0

/* ensure PendSV exception taken place before subsequent operation */
DSB
ISB
Expand Down
11 changes: 9 additions & 2 deletions libcpu/arm/cortex-m4/context_iar.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */

;/**
Expand All @@ -36,7 +37,8 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
PUBWEAK rt_hw_interrupt_disable
SECTION .text:CODE:REORDER:NOROOT(2)
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
Expand All @@ -45,7 +47,8 @@ rt_hw_interrupt_disable:
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
PUBWEAK rt_hw_interrupt_enable
SECTION .text:CODE:REORDER:NOROOT(2)
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
Expand Down Expand Up @@ -208,6 +211,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I

; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0

; ensure PendSV exception taken place before subsequent operation
DSB
ISB
Expand Down
9 changes: 7 additions & 2 deletions libcpu/arm/cortex-m4/context_rvds.S
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2024-08-13 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */

;/**
Expand All @@ -36,7 +37,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
EXPORT rt_hw_interrupt_disable [WEAK]
MRS r0, PRIMASK
CPSID I
BX LR
Expand All @@ -46,7 +47,7 @@ rt_hw_interrupt_disable PROC
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
EXPORT rt_hw_interrupt_enable [WEAK]
MSR PRIMASK, r0
BX LR
ENDP
Expand Down Expand Up @@ -208,6 +209,10 @@ rt_hw_context_switch_to PROC
CPSIE F
CPSIE I

; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0

; ensure PendSV exception taken place before subsequent operation
DSB
ISB
Expand Down