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fix(rocjitsu): Add InstDefUse Checks to Handle Partial Defs #7979

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Merged
theSK2005 merged 7 commits into from
Jul 14, 2026
Merged

fix(rocjitsu): Add InstDefUse Checks to Handle Partial Defs #7979

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f00d7eb
adding liveness checks to handle partial defs
theSK2005 Jun 29, 2026
0ab7507
addressed Allyson and James' comments
theSK2005 Jul 1, 2026
a1a7d4c
pre-commit fix
theSK2005 Jul 1, 2026
02ed915
removed TODO
theSK2005 Jul 6, 2026
222d277
moved MaxLaneWidth to isa_traits.h and changed name to REGISTER_GRANU…
theSK2005 Jul 7, 2026
227b377
moved sub-32 bit src operand coverage to implicit_uses rather than in…
theSK2005 Jul 10, 2026
690530f
Merge branch 'develop' into users/skushwah/liveness-partial-def
theSK2005 Jul 13, 2026
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39 changes: 39 additions & 0 deletions emulation/rocjitsu/lib/python/amdisa/codegen/_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5659,6 +5659,30 @@ def gen_insts(self) -> None:
public_members.append(
cgen.Statement('void execute_impl(amdgpu::Wavefront &wf)')
)
# A sub-dword (< 32-bit) destination writes only part of its
# 32-bit register lane, so the old value survives and the
# register is also a read. Surface these partial defs as
# implicit uses. Runtime-sized outputs are never sub-dword,
# so a static size check suffices. Immediate/label outputs
# (e.g. the S_SETREG hwreg selector) never name a register,
# so skip them to avoid dead overrides.
_partial_def_outputs = [
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o.name
for o in inst.operands
if o.is_output
and operand_size_exprs.get(o.name, str(o.size)) == str(o.size)
and 0 < o.size < 32
and not any(
tag in o.operand_type.upper()
for tag in ('IMM', 'LABEL', 'CONST')
)
]
if _partial_def_outputs:
public_members.append(
cgen.Statement(
'void implicit_uses(RegisterSet &uses) const override'
)
)
if gfx1250_f8f6f4_shape is not None or gfx1250_swmmac_has_modifiers:
public_members.append(
cgen.Statement(
Expand Down Expand Up @@ -6508,6 +6532,21 @@ def _dpp_write_mask_lines(
f'}}'
)
)
if _partial_def_outputs:
_pd_body = ''.join(
f' if (auto r = {name}.to_register_ref())\n'
f' uses.expand(*r);\n'
for name in _partial_def_outputs
)
inst_impls.append(
cgen.Line(
f'void {inst.fmt_name}::implicit_uses'
f'(RegisterSet &uses) const {{\n'
f' {inst.fmt_true_enc_name}::implicit_uses(uses);\n'
f'{_pd_body}'
f'}}'
)
)
inst_impls.append(exec_impl)
class_func_impls.extend(inst_impls)
source_impl_units.append(
Expand Down
4 changes: 0 additions & 4 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/analysis/def_use_chain.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,6 @@ namespace rocjitsu {

namespace {

// TODO: Replace this class-based approximation with instruction metadata that
// identifies vector defs whose inactive lanes are preserved under EXEC, and pair
// it with program-point EXEC state so full-EXEC writes can be treated as normal
// kills.
[[nodiscard]] bool is_exec_masked_def(RegisterRef ref) {
return ref.cls == RegClass::VGPR || ref.cls == RegClass::ACC_VGPR;
}
Expand Down
132 changes: 132 additions & 0 deletions emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna1/vop1.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1119,6 +1119,12 @@ VCvtF16F32Vop1::VCvtF16F32Vop1(const MachineInst *inst)
}
}

void VCvtF16F32Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtF16F32Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -6764,6 +6770,12 @@ VCvtF16U16Vop1::VCvtF16U16Vop1(const MachineInst *inst)
}
}

void VCvtF16U16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtF16U16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -6885,6 +6897,12 @@ VCvtF16I16Vop1::VCvtF16I16Vop1(const MachineInst *inst)
}
}

void VCvtF16I16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtF16I16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7006,6 +7024,12 @@ VCvtU16F16Vop1::VCvtU16F16Vop1(const MachineInst *inst)
}
}

void VCvtU16F16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7127,6 +7151,12 @@ VCvtI16F16Vop1::VCvtI16F16Vop1(const MachineInst *inst)
}
}

void VCvtI16F16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7248,6 +7278,12 @@ VRcpF16Vop1::VRcpF16Vop1(const MachineInst *inst)
}
}

void VRcpF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VRcpF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7381,6 +7417,12 @@ VSqrtF16Vop1::VSqrtF16Vop1(const MachineInst *inst)
}
}

void VSqrtF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VSqrtF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7514,6 +7556,12 @@ VRsqF16Vop1::VRsqF16Vop1(const MachineInst *inst)
}
}

void VRsqF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VRsqF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7647,6 +7695,12 @@ VLogF16Vop1::VLogF16Vop1(const MachineInst *inst)
}
}

void VLogF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VLogF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7780,6 +7834,12 @@ VExpF16Vop1::VExpF16Vop1(const MachineInst *inst)
}
}

void VExpF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VExpF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -7913,6 +7973,12 @@ VFrexpMantF16Vop1::VFrexpMantF16Vop1(const MachineInst *inst)
}
}

void VFrexpMantF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VFrexpMantF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8046,6 +8112,12 @@ VFrexpExpI16F16Vop1::VFrexpExpI16F16Vop1(const MachineInst *inst)
}
}

void VFrexpExpI16F16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VFrexpExpI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8179,6 +8251,12 @@ VFloorF16Vop1::VFloorF16Vop1(const MachineInst *inst)
}
}

void VFloorF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VFloorF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8312,6 +8390,12 @@ VCeilF16Vop1::VCeilF16Vop1(const MachineInst *inst)
}
}

void VCeilF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCeilF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8445,6 +8529,12 @@ VTruncF16Vop1::VTruncF16Vop1(const MachineInst *inst)
}
}

void VTruncF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VTruncF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8578,6 +8668,12 @@ VRndneF16Vop1::VRndneF16Vop1(const MachineInst *inst)
}
}

void VRndneF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VRndneF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8711,6 +8807,12 @@ VFractF16Vop1::VFractF16Vop1(const MachineInst *inst)
}
}

void VFractF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VFractF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8844,6 +8946,12 @@ VSinF16Vop1::VSinF16Vop1(const MachineInst *inst)
}
}

void VSinF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VSinF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -8977,6 +9085,12 @@ VCosF16Vop1::VCosF16Vop1(const MachineInst *inst)
}
}

void VCosF16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCosF16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -9110,6 +9224,12 @@ VCvtNormI16F16Vop1::VCvtNormI16F16Vop1(const MachineInst *inst)
}
}

void VCvtNormI16F16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtNormI16F16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -9243,6 +9363,12 @@ VCvtNormU16F16Vop1::VCvtNormU16F16Vop1(const MachineInst *inst)
}
}

void VCvtNormU16F16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VCvtNormU16F16Vop1::execute_impl(amdgpu::Wavefront &wf) {
uint32_t sdwa_old_dst_[64] = {};
if (sdwa_dst_sel_ != amdgpu::sdwa::DWORD || inst_.src0 == amdgpu::SRC_DPP) {
Expand Down Expand Up @@ -9376,6 +9502,12 @@ VSatPkU8I16Vop1::VSatPkU8I16Vop1(const MachineInst *inst)
}
}

void VSatPkU8I16Vop1::implicit_uses(RegisterSet &uses) const {
Vop1::implicit_uses(uses);
if (auto r = vdst.to_register_ref())
uses.expand(*r);
}

void VSatPkU8I16Vop1::execute_impl(amdgpu::Wavefront &wf) {
(void)wf;
throw util::UnimplementedInst(mnemonic());
Expand Down
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