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Pull request overview
This PR updates rocjitsu’s RDNA3/RDNA4/GFX11+ dispatch setup to correctly handle packed workitem IDs and wave-size-dependent VGPR descriptor decoding, and expands unit/simulation coverage for these behaviors. It also extends per-process GPU VA translation usage in a few runtime paths (e.g., kernarg preload, Tensor DMA) and introduces additional barrier semantics in wavefront/CU state handling.
Changes:
- Enable/consume packed workitem IDs on RDNA3/RDNA3.5/RDNA4 and decode VGPR counts using wave-size-specific GFX11+ descriptor granularity.
- Plumb per-dispatch wave size through dispatch entry → CU dispatch, and adjust VGPR storage assumptions to support wave32 vs wave64 dispatches.
- Add/extend tests for packed TID-in-v0 (including one-TID-VGPR case), per-process memory mappings (dmabuf/userptr), and split-barrier behavior.
Reviewed changes
Copilot reviewed 23 out of 23 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.cpp | Wave-size aware dispatch setup (packed TID init, VGPR granularity decode, grid WG rounding) and SDMA dialect adjustments |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/command_processor.h | Add Gfx1250 SDMA dialect and helpers |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.cpp | Dispatch wavefronts with per-dispatch wave size; update barrier state handling |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/compute_unit.h | Switch VGPR storage to fixed 64-lane regs; expose vgpr_lanes_per_reg; wave-size plumb-through |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/wavefront.h | Add split-barrier state/generation tracking; waitcnt name aliases; vcc_live_lanes |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/spi.h | Pass wave size into CU dispatch and exec mask computation |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/dispatch_entry.h | Track per-dispatch wave size |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/gpu_memory.h | Add bulk read/write APIs and read/write-aware translation paths |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/kfd_process.h | Track host read/write accessibility in PTEs; add host mapping access checks |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/kmd/linux/simulated_driver.cpp | Track host_ptr ownership; map imported dmabufs to real backing; fix unmap behavior |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/shared/tensor_dma.h | Use wave/process VMID for global memory accesses |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/l2_cache.cpp | Use GpuMemory bulk byte read/write for backing accesses |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/vm/amdgpu/hbm_controller.h | Use GpuMemory bulk byte read/write |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/config_loader.cpp | Enable packed_tid for RDNA3/3.5/4; select Gfx1250 SDMA dialect explicitly |
| emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/config/checkpoint.cpp | Restore wavefronts with inferred wave size and updated dispatch API |
| emulation/rocjitsu/lib/util/include/util/data_types.h | FP8 E4M3 overflow/Inf handling updated to produce NaN encoding |
| emulation/rocjitsu/tests/config_test.cpp | Update expectations for packed_tid on RDNA3/4 |
| emulation/rocjitsu/tests/data_types_test.cpp | Update FP8 tests for NaN-on-overflow/Inf behavior |
| emulation/rocjitsu/tests/aql_queue.h | Allow setting queue process_id in the test AQL queue wrapper |
| emulation/rocjitsu/tests/kfd_ioctl_test.cpp | Add dmabuf backing-at-GPU-VA and unaligned userptr mapping coverage |
| emulation/rocjitsu/tests/amdgpu_vm_test.cpp | Add passthrough pointer access fallback tests |
| emulation/rocjitsu/tests/gfx1250_sim_test.cpp | Add Tensor DMA per-process mapping test; add packed-tid wave32 coverage; update SDMA dialect expectation |
| emulation/rocjitsu/tests/shared_infra_test.cpp | Add split-barrier behavior test |
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amd-eochoalo
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Groverkss
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Make RDNA3/RDNA4 simulation run smoke-test kernels by carrying the runtime metadata and memory behavior that those kernels rely on: descriptor wave size, per-dispatch workgroup geometry, wave32/wave64 VGPR storage, process VMID memory, host USERPTR permissions, and the gfx12 SDMA packet dialect. Keep live host VMA permissions synchronized without parsing /proc/self/maps on every translation by invalidating cached snapshots from the interposer after successful mmap, mprotect, and munmap calls. In daemon mode, forward synthetic DRM mmap requests through the remote KFD driver so imported dma-buf mappings get real host backing. Also remove stale GPU VM mappings on allocation free, mask multidimensional partial-grid EXEC lanes per lane, preserve mmap errno behavior, serialize 64-lane VGPR checkpoints, and keep E4M3FN NaN/overflow handling consistent across converters. Adds regression coverage for RDNA/GFX1250 dispatch setup, partial grids, host page-table permissions, dmabuf import/free, checkpoint restore, and FP8 special values.
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## Motivation This extends RocJITsu’s generated AMDGPU ISA support so RDNA3/RDNA3.5/RDNA4 simulation can execute the instruction patterns needed by IREE e2e tests and the fpsan numeric suite. The bulk of the diff is regenerated ISA output. The source changes are concentrated in the Python generator/profile logic, shared execution helpers, and regression tests. This needs #7625 to work e2e. ## Technical Details - Add generator-backed execution coverage for RDNA packed/vector paths: - packed 16-bit source/destination handling - true16 VOP3 `op_sel` handling - DPP-aware VOP3 paths - VOP3/VOP3P dot, compare, convert, and mixed-width operations - Add RDNA WMMA/SWMMAC dispatch support: - RDNA3/RDNA3.5 GFX11 WMMA layout - RDNA4 GFX12 WMMA/SWMMAC layout - FP8/BF8/F16/BF16/IU matrix paths needed by smoke kernels - Fix RDNA4 compatibility behavior: - inject opcode-9 `s_waitcnt` compatibility form where the XML only exposes split wait instructions - keep execution and disassembly formatting on the same GFX11 waitcnt bit layout - preserve generated decode/format tests for nonzero waitcnt immediates - Refresh generated outputs from the same generator state: - RDNA3/RDNA3.5/RDNA4 generated ISA files - gfx1250 generated VOP3 split files - DBT legalization tables - Expand regression coverage: - generator/profile tests for RDNA feature gates and matrix dispatch wiring - decode and execution harness tests for RDNA/RDNA4 paths - SIMD correctness coverage for wide MAD/shift behavior - value-level tests for dot2, SCC overflow, true16 modifiers, and waitcnt formatting ## JIRA ID N/A ## Test Plan Unit tests, IREE e2e tests, fpsan tests across rdan3, rdna4, and gfx1250. Rerun the generator across all ISAs. ## Test Result All good with the runtime patch. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.
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I'm going to close this because @atgutier should have a more comprehensive set of fixes that subsumes this |
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This should be ported over to https://github.com/ROCm/rocm-systems/tree/users/agutierr/rj-hrx-systems-fixes-wip |
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Motivation
IREE-emitted RDNA kernels rely on packed TID values in v0, and wave64 RDNA descriptors encode VGPR counts differently from the runtime’s previous fixed granularity assumption. Without these fixes, dispatch setup can initialize the wrong workitem IDs or under/overcompute VGPR allocation, causing otherwise valid RDNA3/RDNA4 kernels to fail in simulation.
Technical Details
The interposer now keeps the simulator’s view of host VMAs in sync with process mapping changes. GPU page-table entries can point at USERPTR or imported dma-buf host mappings, but those mappings may later become
PROT_NONE, read-only, or unmapped. After successfulmmap,mprotect, andmunmapcalls, the interposer invalidates the cached host-mapping snapshot so GPU memory translation can refresh permissions and fall back to sparse simulator memory instead of dereferencing inaccessible host pages.In the daemon mode, synthetic DRM fds do not have local mmap state, so DRM mmap requests are forwarded through the remote KFD driver. This gives imported dma-buf mappings real host backing while preserving the same host-VMA permission tracking path as local simulation.
JIRA ID
N/A
Test Plan
Unit tests + local smoke tests.
Test Result
All good.
Submission Checklist