rocjitsu: Harden ISA layer, virtual machine, and adds initial DBT

experimental/rocjitsu/.gitignore

@@ -20,15 +20,17 @@
 *.out
 *.app
 
+# Misc local working artifacts
 *.swp
 .vscode
 build
 third_party
 Testing
+tmp
 
 # python
-.venv/
-__pycache__/
+.venv
+__pycache__
 *.pyc
 *.pyo
 *.pyd

experimental/rocjitsu/README.md

@@ -39,6 +39,9 @@ applications.
 - **ISA Code Generation** - instruction decoders and execution bodies are
   generated from the [Machine-Readable ISA (MR ISA)](https://gpuopen.com/machine-readable-isa/) XML
   spec via a Python library (`amdisa`).
+- **Dynamic Binary Translation** - cross-ISA instruction legalization tables
+  and encoding translator data tables are auto-generated by `amdisa` from
+  the MR ISA XML specs, enabling translation between any supported ISA pair.
 - **GUI** - optional topology visualizer and timeline viewer.
 - **Configuration** - JSON configs validated against FlatBuffers schemas for
   topology, programs, and simulation parameters.
@@ -61,8 +64,10 @@ lib/
       code/             Executable loader, code object, basic block analysis
       config/           JSON/FlatBuffers config loading, topology builder, checkpointing
       isa/              ISA framework (decoder, instruction, operand)
-        arch/amdgpu/    AMDGPU ISA (CDNA3/CDNA4, mostly autogenerated)
+        arch/amdgpu/    AMDGPU ISA (all 9 targets, mostly autogenerated)
         arch/risc_v/    RISC-V ISA (RV32IMAFDC)
+        dbt/            Encoding translator engine and coherency remap helpers
+        dbt/generated/  Auto-generated legalization tables and encoding translation data tables
       vm/               Virtual machine layer
         amdgpu/         AMD GPU hardware model (CU, SE, XCD, caches, pipelines)
         risc_v/         RISC-V hart model
@@ -283,6 +288,47 @@ not overwritten by the generator.
 
 You can find the MR ISA in the artifacts directory.
 
+### Regenerating DBT files
+
+The cross-ISA legalization tables and encoding translator data tables are also
+autogenerated from the MR ISA XML specs. These are used by the dynamic binary
+translation (DBT) subsystem.
+
+```bash
+# Legalization tables (all supported ISA pairs)
+PYTHONPATH=$PWD/lib/python python3 -m amdisa --multi \
+  cdna1:$MRISA/amdgpu_isa_cdna1.xml \
+  cdna2:$MRISA/amdgpu_isa_cdna2.xml \
+  cdna3:$MRISA/amdgpu_isa_cdna3.xml \
+  cdna4:$MRISA/amdgpu_isa_cdna4.xml \
+  rdna1:$MRISA/amdgpu_isa_rdna1.xml \
+  rdna2:$MRISA/amdgpu_isa_rdna2.xml \
+  rdna3:$MRISA/amdgpu_isa_rdna3.xml \
+  rdna3_5:$MRISA/amdgpu_isa_rdna3_5.xml \
+  rdna4:$MRISA/amdgpu_isa_rdna4.xml \
+  --gen-legalization \
+  --legalization-output lib/rocjitsu/src/rocjitsu/code/dbt/generated
+
+# Encoding field structs (all ISAs) + translators (one pair)
+PYTHONPATH=$PWD/lib/python python3 -m amdisa --multi \
+  cdna1:$MRISA/amdgpu_isa_cdna1.xml \
+  cdna2:$MRISA/amdgpu_isa_cdna2.xml \
+  cdna3:$MRISA/amdgpu_isa_cdna3.xml \
+  cdna4:$MRISA/amdgpu_isa_cdna4.xml \
+  rdna1:$MRISA/amdgpu_isa_rdna1.xml \
+  rdna2:$MRISA/amdgpu_isa_rdna2.xml \
+  rdna3:$MRISA/amdgpu_isa_rdna3.xml \
+  rdna3_5:$MRISA/amdgpu_isa_rdna3_5.xml \
+  rdna4:$MRISA/amdgpu_isa_rdna4.xml \
+  --gen-encoding-translators --encoding-pair "cdna4->rdna4" \
+  --encoding-translator-output lib/rocjitsu/src/rocjitsu/code/dbt/generated
+
+# Format generated files
+./scripts/clang_format.sh lib/rocjitsu/src/rocjitsu/code/dbt/
+```
+
+See `lib/python/amdisa/README.md` for details on the amdisa codegen pipeline.
+
 ## Usage examples
 
 ### Run a simulation

experimental/rocjitsu/configs/amdgpu_cdna3.json

@@ -0,0 +1,118 @@
+{
+  "max_ticks": 100000,
+  "num_threads": 1,
+  "exec_mode": "functional",
+  "vm": {
+    "arch": "cdna3",
+    "gpu": {
+      "device": {
+        "gpu_id": 50148,
+        "gfx_target_version": 90402,
+        "vendor_id": 4098,
+        "device_id": 29856,
+        "family_id": 146,
+        "unique_id": 0,
+        "marketing_name": "AMD Instinct MI300X",
+        "simd_count": 1216,
+        "max_waves_per_simd": 8,
+        "num_shader_engines": 4,
+        "num_shader_arrays_per_engine": 2,
+        "num_cu_per_sh": 5,
+        "simd_per_cu": 4,
+        "wave_front_size": 64,
+        "local_mem_size": 206158430208,
+        "lds_size_kb": 64,
+        "mem_width": 8192,
+        "mem_clk_max": 1300,
+        "l2_size_kb": 4096,
+        "num_sdma_engines": 4,
+        "num_sdma_xgmi_engines": 6,
+        "num_cp_queues": 128,
+        "max_engine_clk_fcompute": 2100
+      }
+    }
+  },
+  "topology": {
+    "root": {
+      "name": "soc", "type": "soc",
+      "children": [
+        { "name": "vram", "type": "gpu_memory" },
+        {
+          "name": "iod[0:4]", "type": "iod",
+          "config": [{ "key": "num_hbm_stacks", "value": "2" }]
+        },
+        {
+          "name": "xcd[0:8]", "type": "xcd",
+          "children": [
+            { "name": "l2", "type": "l2_cache" },
+            { "name": "cp", "type": "command_processor" },
+            {
+              "name": "se[0:4]", "type": "shader_engine",
+              "children": [{
+                "name": "cu[0:8]", "type": "compute_unit",
+                "config": [
+                  { "key": "num_wf_slots", "value": "32" },
+                  { "key": "sgprs_per_wf", "value": "104" },
+                  { "key": "vgprs_per_wf", "value": "512" },
+                  { "key": "lds_size_kb", "value": "64" }
+                ]
+              }]
+            }
+          ]
+        }
+      ]
+    },
+    "links": [
+      {
+        "pattern": "xcd[i].cp.req_[j*8+k] -> xcd[i].se[j].cu[k].cpl",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 8 },
+          { "var_name": "j", "start": 0, "end": 4 },
+          { "var_name": "k", "start": 0, "end": 8 }
+        ],
+        "latency": 1, "weight": 2
+      },
+      {
+        "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*8+k]",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 8 },
+          { "var_name": "j", "start": 0, "end": 4 },
+          { "var_name": "k", "start": 0, "end": 8 }
+        ],
+        "latency": 1, "weight": 10
+      },
+      {
+        "pattern": "xcd[i].l2.req -> iod[i/2].msc.cpl_[i%2]",
+        "for_ranges": [{ "var_name": "i", "start": 0, "end": 8 }],
+        "latency": 1, "weight": 3
+      },
+      {
+        "pattern": "iod[i].peer_req -> iod[j].peer_cpl",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 4 },
+          { "var_name": "j", "start": 0, "end": 4 }
+        ],
+        "where_expr": "i != j",
+        "latency": 1, "weight": 1
+      },
+      {
+        "pattern": "xcd[i].se[j].cu[k].adj_req -> xcd[i].se[j].cu[k+1].adj_cpl",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 8 },
+          { "var_name": "j", "start": 0, "end": 4 },
+          { "var_name": "k", "start": 0, "end": 7 }
+        ],
+        "latency": 1, "weight": 2
+      },
+      {
+        "pattern": "xcd[i].se[j].cu[k+1].adj_req_r -> xcd[i].se[j].cu[k].adj_cpl_r",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 8 },
+          { "var_name": "j", "start": 0, "end": 4 },
+          { "var_name": "k", "start": 0, "end": 7 }
+        ],
+        "latency": 1, "weight": 2
+      }
+    ]
+  }
+}

experimental/rocjitsu/configs/amdgpu_cdna3_kmd.json

@@ -0,0 +1,89 @@
+{
+  "max_ticks": 100000,
+  "num_threads": 1,
+  "exec_mode": "functional",
+  "vm": {
+    "arch": "cdna3",
+    "gpu": {
+      "device": {
+        "gpu_id": 50148,
+        "gfx_target_version": 90402,
+        "vendor_id": 4098,
+        "device_id": 29856,
+        "family_id": 146,
+        "unique_id": 0,
+        "marketing_name": "AMD Instinct MI300X",
+        "drm_render_minor": 128,
+        "simd_count": 16,
+        "max_waves_per_simd": 8,
+        "num_shader_engines": 1,
+        "num_shader_arrays_per_engine": 1,
+        "num_cu_per_sh": 4,
+        "simd_per_cu": 4,
+        "wave_front_size": 64,
+        "max_slots_scratch_cu": 32,
+        "local_mem_size": 206158430208,
+        "lds_size_kb": 64,
+        "mem_width": 8192,
+        "mem_clk_max": 1300,
+        "l1_size_kb": 32,
+        "l1_line_size": 128,
+        "l1_assoc": 4,
+        "l2_size_kb": 4096,
+        "l2_line_size": 128,
+        "l2_assoc": 16,
+        "num_sdma_engines": 4,
+        "num_sdma_xgmi_engines": 6,
+        "num_cp_queues": 128,
+        "max_engine_clk_fcompute": 2100
+      }
+    }
+  },
+  "topology": {
+    "root": {
+      "name": "soc", "type": "soc",
+      "children": [
+        { "name": "vram", "type": "gpu_memory" },
+        {
+          "name": "xcd[0:1]", "type": "xcd",
+          "children": [
+            { "name": "l2", "type": "l2_cache" },
+            { "name": "cp", "type": "command_processor" },
+            {
+              "name": "se[0:1]", "type": "shader_engine",
+              "children": [{
+                "name": "cu[0:4]", "type": "compute_unit",
+                "config": [
+                  { "key": "num_wf_slots", "value": "32" },
+                  { "key": "sgprs_per_wf", "value": "104" },
+                  { "key": "vgprs_per_wf", "value": "512" },
+                  { "key": "lds_size_kb", "value": "64" }
+                ]
+              }]
+            }
+          ]
+        }
+      ]
+    },
+    "links": [
+      {
+        "pattern": "xcd[i].cp.req_[j*4+k] -> xcd[i].se[j].cu[k].cpl",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 1 },
+          { "var_name": "j", "start": 0, "end": 1 },
+          { "var_name": "k", "start": 0, "end": 4 }
+        ],
+        "latency": 1, "weight": 2
+      },
+      {
+        "pattern": "xcd[i].se[j].cu[k].req -> xcd[i].l2.cpl_[j*4+k]",
+        "for_ranges": [
+          { "var_name": "i", "start": 0, "end": 1 },
+          { "var_name": "j", "start": 0, "end": 1 },
+          { "var_name": "k", "start": 0, "end": 4 }
+        ],
+        "latency": 1, "weight": 10
+      }
+    ]
+  }
+}

experimental/rocjitsu/configs/amdgpu_cdna4.json

@@ -14,17 +14,17 @@
         "unique_id": 5929628898254127105,
         "marketing_name": "AMD Instinct MI350X",
         "simd_count": 1024,
-        "max_waves_per_simd": 10,
+        "max_waves_per_simd": 8,
         "num_shader_engines": 4,
         "num_shader_arrays_per_engine": 2,
         "num_cu_per_sh": 4,
         "simd_per_cu": 4,
         "wave_front_size": 64,
         "local_mem_size": 309237645312,
-        "lds_size_kb": 128,
+        "lds_size_kb": 160,
         "mem_width": 8192,
         "mem_clk_max": 1600,
-        "l2_size_kb": 6144,
+        "l2_size_kb": 4096,
         "num_sdma_engines": 5,
         "num_sdma_xgmi_engines": 12,
         "num_cp_queues": 128,
@@ -51,7 +51,7 @@
               "children": [{
                 "name": "cu[0:8]", "type": "compute_unit",
                 "config": [
-                  { "key": "num_wf_slots", "value": "40" },
+                  { "key": "num_wf_slots", "value": "32" },
                   { "key": "sgprs_per_wf", "value": "104" },
                   { "key": "vgprs_per_wf", "value": "512" },
                   { "key": "lds_size_kb", "value": "160" }

experimental/rocjitsu/configs/amdgpu_cdna4_kmd.json

@@ -5,7 +5,6 @@
   "vm": {
     "arch": "cdna4",
     "gpu": {
-      "num_xcds": 2,
       "device": {
         "gpu_id": 38144,
         "gfx_target_version": 90500,
@@ -15,22 +14,22 @@
         "unique_id": 5929628898254127105,
         "marketing_name": "AMD Instinct MI350X",
         "drm_render_minor": 128,
-        "simd_count": 256,
-        "max_waves_per_simd": 10,
+        "simd_count": 1024,
+        "max_waves_per_simd": 8,
         "num_shader_engines": 4,
         "num_shader_arrays_per_engine": 2,
         "num_cu_per_sh": 4,
         "simd_per_cu": 4,
         "wave_front_size": 64,
         "max_slots_scratch_cu": 32,
         "local_mem_size": 309237645312,
-        "lds_size_kb": 128,
+        "lds_size_kb": 160,
         "mem_width": 8192,
         "mem_clk_max": 1600,
         "l1_size_kb": 32,
         "l1_line_size": 128,
         "l1_assoc": 4,
-        "l2_size_kb": 6144,
+        "l2_size_kb": 4096,
         "l2_line_size": 128,
         "l2_assoc": 16,
         "num_sdma_engines": 5,
@@ -55,7 +54,7 @@
               "children": [{
                 "name": "cu[0:4]", "type": "compute_unit",
                 "config": [
-                  { "key": "num_wf_slots", "value": "40" },
+                  { "key": "num_wf_slots", "value": "32" },
                   { "key": "sgprs_per_wf", "value": "104" },
                   { "key": "vgprs_per_wf", "value": "512" },
                   { "key": "lds_size_kb", "value": "160" }