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fix(rocrtst): Fix MemoryAccessCoherent AQL queue submission - #13530

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users/fcui/wsl_aql_MemoryAccessCoherentTes
Nov 4, 2026
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erman-gurses merged 1 commit into
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users/fcui/wsl_aql_MemoryAccessCoherentTes

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Motivation

MemoryAccessCoherentTest enqueues a barrier-AND packet and a kernel dispatch, then rings the queue doorbell so a host-to-device copy, the shader, and a device-to-host copy run in order. The barrier header was published with the packet body, and the doorbell was rung with the queue write index after both packets had already advanced it. The command processor can then see an incomplete barrier packet or a doorbell value one slot past the last written packet, so the coherent copy sequence does not complete.

Technical Details

  • The barrier-AND packet is copied into the queue with its header still invalid. rocrtst::AtomicSetPacketHeader then release-stores the packet type, matching the dispatch path and GPUAccessToCPUMemoryTest in the same file.
  • The kernel-dispatch slot is kept in dispatch_index. The doorbell is stored with that index, the last packet written, instead of a write index reloaded after the queue has already been advanced past it.

Issue Tracking

Test Plan

Run the rocrtst memory-access functional suite and confirm MemoryAccessCoherentTest completes

Test Result

Submission Checklist

@fcui-amd
fcui-amd marked this pull request as ready for review October 15, 2026 07:53
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📝 PR Description ❌ Fail Error: PR description must reference a JIRA ID, ISSUE ID, or a GitHub closing keyword.
Expected: include a JIRA ID / ISSUE ID line (separator : or -, or omitted; value may be a JIRA key, a number with/without #, or a link), OR a closing keyword + issue reference. Accepted examples:
• JIRA ID : TESTAUTO-6039
• JIRA ID - #330
• JIRA ID #330
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ROCM-25757
• ISSUE ID : TESTUTO-3334
• ISSUE ID #3334
• ISSUE ID - TESTAUTO-3433
• ISSUE ID (on separate line)
AIRUNTIME-2352
• ISSUE ID : https://github.com/<org_name>/<repo_name>/issues/1234
• Closes #10
• Fixes octo-org/octo-repo#100
• Resolves: #123
• #123
• https://github.com/<org_name>/<repo_name>/issues/123
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Expected: add at least one test file named like test_<name>.py / test_<name>.cpp (or <name>_test.*).
Current: code file(s) changed: projects/rocr-runtime/rocrtst/suites/functional/memory_access.cc; no test file found
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🚫 Please fix the failed policies before requesting reviews.

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ping?

@shwetagkhatri shwetagkhatri left a comment

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LGTM

Signed-off-by: Flora Cui <flora.cui@amd.com>
@shwetagkhatri
shwetagkhatri force-pushed the users/fcui/wsl_aql_MemoryAccessCoherentTes branch from d9b8cd4 to 43bfee9 Compare November 2, 2026 19:45
@erman-gurses
erman-gurses merged commit abb49fb into develop Nov 4, 2026
352 of 359 checks passed
@erman-gurses
erman-gurses deleted the users/fcui/wsl_aql_MemoryAccessCoherentTes branch November 4, 2026 03:14
systems-assistant Bot pushed a commit to ROCm/ROCR-Runtime that referenced this pull request Nov 4, 2026
 (#13530)

## Motivation

MemoryAccessCoherentTest enqueues a barrier-AND packet and a kernel
dispatch, then rings the queue doorbell so a host-to-device copy, the
shader, and a device-to-host copy run in order. The barrier header was
published with the packet body, and the doorbell was rung with the queue
write index after both packets had already advanced it. The command
processor can then see an incomplete barrier packet or a doorbell value
one slot past the last written packet, so the coherent copy sequence
does not complete.

## Technical Details

- The barrier-AND packet is copied into the queue with its header still
invalid. rocrtst::AtomicSetPacketHeader then release-stores the packet
type, matching the dispatch path and GPUAccessToCPUMemoryTest in the
same file.
- The kernel-dispatch slot is kept in dispatch_index. The doorbell is
stored with that index, the last packet written, instead of a write
index reloaded after the queue has already been advanced past it.

## Issue Tracking

<!-- Include a GitHub Issue and/or JIRA ID. Do not post any full JIRA
links here. -->
<!-- GitHub issue: ROCm/rocm-systems#1234 -->
<!-- JIRA ID: EXAMPLECOMPONENT-1234 -->

## Test Plan

Run the rocrtst memory-access functional suite and confirm
MemoryAccessCoherentTest completes

## Test Result

<!-- Briefly summarize test outcomes. -->

## Submission Checklist

- [ ] Look over the contributing guidelines at
https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md.

Signed-off-by: Flora Cui <flora.cui@amd.com>
[rocm-systems] ROCm/rocm-systems#13530 (commit abb49fb)
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3 participants