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fix(rocrtst): Fix MemoryAccessCoherent AQL queue submission - #13530
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Signed-off-by: Flora Cui <flora.cui@amd.com>
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(#13530) ## Motivation MemoryAccessCoherentTest enqueues a barrier-AND packet and a kernel dispatch, then rings the queue doorbell so a host-to-device copy, the shader, and a device-to-host copy run in order. The barrier header was published with the packet body, and the doorbell was rung with the queue write index after both packets had already advanced it. The command processor can then see an incomplete barrier packet or a doorbell value one slot past the last written packet, so the coherent copy sequence does not complete. ## Technical Details - The barrier-AND packet is copied into the queue with its header still invalid. rocrtst::AtomicSetPacketHeader then release-stores the packet type, matching the dispatch path and GPUAccessToCPUMemoryTest in the same file. - The kernel-dispatch slot is kept in dispatch_index. The doorbell is stored with that index, the last packet written, instead of a write index reloaded after the queue has already been advanced past it. ## Issue Tracking <!-- Include a GitHub Issue and/or JIRA ID. Do not post any full JIRA links here. --> <!-- GitHub issue: ROCm/rocm-systems#1234 --> <!-- JIRA ID: EXAMPLECOMPONENT-1234 --> ## Test Plan Run the rocrtst memory-access functional suite and confirm MemoryAccessCoherentTest completes ## Test Result <!-- Briefly summarize test outcomes. --> ## Submission Checklist - [ ] Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md. Signed-off-by: Flora Cui <flora.cui@amd.com> [rocm-systems] ROCm/rocm-systems#13530 (commit abb49fb)
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Motivation
MemoryAccessCoherentTest enqueues a barrier-AND packet and a kernel dispatch, then rings the queue doorbell so a host-to-device copy, the shader, and a device-to-host copy run in order. The barrier header was published with the packet body, and the doorbell was rung with the queue write index after both packets had already advanced it. The command processor can then see an incomplete barrier packet or a doorbell value one slot past the last written packet, so the coherent copy sequence does not complete.
Technical Details
Issue Tracking
Test Plan
Run the rocrtst memory-access functional suite and confirm MemoryAccessCoherentTest completes
Test Result
Submission Checklist