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[rocjitsu] Isolate cache locks to reduce false sharing - #13109
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Align L2 set mutexes and sparse-memory page stripes to 64-byte boundaries so independent accesses do not write the same host cache line. Preserve set-range deduplication, lock ordering and existing mutex protocols. On Linux x86-64, add 48 KiB per L2Cache and 16,408 bytes per SparseMemory. Across three perf captures with 32 pinned workers, controlled probes show the following reductions: | Probe | User cycles | L2 store/state-change requests | | --- | ---: | ---: | | L2 adjacent locks | 72.5% | 83.7% | | Sparse adjacent reads | 53.6% | 53.1% | Sparse-read instruction counts are unchanged. Spaced controls show no cycle benefit. Probe counters include setup and teardown. These probes force adjacent lock or stripe indices. The sparse page hash makes adjacent stripes uncommon for sequential pages. The probes show the mechanism; the application results below measure both changes together and do not establish either change's individual contribution. For an actual HIP gather over 4,194,304 floats on simulated gfx1250 with 48 host cores, the five-pair screen gives 1.056x process and 1.093x warm speedups. Ten fresh interleaved pairs confirm 1.045x process and 1.091x warm speedups. Descriptive paired bootstrap 95% intervals are 1.007-1.084x and 1.043-1.150x, respectively. Compare against develop 923570c with matching Clang 23 Release -O3, x86-64-v4 builds on reserved Threadripper PRO 9995WX cores. Process time includes startup and validation; warm time is the median of five launch-plus-synchronization samples after one warmup. Report paired geometric means. The gather validates every output element. Twenty-pair gfx1201 and gfx950 IREE checks give 1.021x and 0.994x process ratios. Other results are small or inconclusive; this does not establish a general simulator speedup. Validation: 412 focused native tests and 260 measured processes pass their checks. The existing L2 admission suite also passes 45 GCC 13 TSan test executions. A broader 37-case five-target smoke matrix also passes (correctness only, run concurrently with review). Pre-commit passes for both changed headers.
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Align L2 set mutexes and sparse-memory page stripes to 64-byte boundaries so independent accesses do not write the same host cache line. Preserve set-range deduplication, lock ordering and existing mutex protocols. On Linux x86-64, add 48 KiB per L2Cache and 16,408 bytes per SparseMemory. Across three perf captures with 32 pinned workers, controlled probes show the following reductions: | Probe | User cycles | L2 store/state-change requests | | --- | ---: | ---: | | L2 adjacent locks | 72.5% | 83.7% | | Sparse adjacent reads | 53.6% | 53.1% | Sparse-read instruction counts are unchanged. Spaced controls show no cycle benefit. Probe counters include setup and teardown. These probes force adjacent lock or stripe indices. The sparse page hash makes adjacent stripes uncommon for sequential pages. The probes show the mechanism; the application results below measure both changes together and do not establish either change's individual contribution. For an actual HIP gather over 4,194,304 floats on simulated gfx1250 with 48 host cores, the five-pair screen gives 1.056x process and 1.093x warm speedups. Ten fresh interleaved pairs confirm 1.045x process and 1.091x warm speedups. Descriptive paired bootstrap 95% intervals are 1.007-1.084x and 1.043-1.150x, respectively. Compare against develop 923570c with matching Clang 23 Release -O3, x86-64-v4 builds on reserved Threadripper PRO 9995WX cores. Process time includes startup and validation; warm time is the median of five launch-plus-synchronization samples after one warmup. Report paired geometric means. The gather validates every output element. Twenty-pair gfx1201 and gfx950 IREE checks give 1.021x and 0.994x process ratios. Other results are small or inconclusive; this does not establish a general simulator speedup. Validation: 412 focused native tests and 260 measured processes pass their checks. The existing L2 admission suite also passes 45 GCC 13 TSan test executions. A broader 37-case five-target smoke matrix also passes (correctness only, run concurrently with review). Pre-commit passes for both changed headers.
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Align L2 set mutexes and sparse-memory page stripes to 64-byte boundaries so independent accesses do not write the same host cache line. Preserve set-range deduplication, lock ordering and existing mutex protocols.
On Linux x86-64, add 48 KiB per L2Cache and 16,408 bytes per SparseMemory. Across three perf captures with 32 pinned workers, controlled probes show the following reductions:
Sparse-read instruction counts are unchanged. Spaced controls show no cycle benefit. Probe counters include setup and teardown. These probes force adjacent lock or stripe indices. The sparse page hash makes adjacent stripes uncommon for sequential pages. The probes show the mechanism; the application results below measure both changes together and do not establish either change's individual contribution.
For an actual HIP gather over 4,194,304 floats on simulated gfx1250 with 48 host cores, the five-pair screen gives 1.056x process and 1.093x warm speedups. Ten fresh interleaved pairs confirm 1.045x process and 1.091x warm speedups. Descriptive paired bootstrap 95% intervals are 1.007-1.084x and 1.043-1.150x, respectively.
Compare against develop 923570c with matching Clang 23 Release -O3, x86-64-v4 builds on reserved Threadripper PRO 9995WX cores. Process time includes startup and validation; warm time is the median of five launch-plus-synchronization samples after one warmup. Report paired geometric means. The gather validates every output element.
Twenty-pair gfx1201 and gfx950 IREE checks give 1.021x and 0.994x process ratios. Other results are small or inconclusive; this does not establish a general simulator speedup.
Validation: 412 focused native tests and 260 measured processes pass their checks. The existing L2 admission suite also passes 45 GCC 13 TSan test executions. A broader 37-case five-target smoke matrix also passes (correctness only, run concurrently with review). Pre-commit passes for both changed headers.