rocjitsu: use SIMD words and set-bit iteration for register sets

emulation/rocjitsu/docs/dbi-design.md

@@ -301,11 +301,13 @@ public:
 
 ### RegisterRef / RegisterSet [shared with DBT]
 
-**Files:** `isa/register_set.h`, `isa/register_set.cpp`
+**File:** `isa/register_set.h`
 **Used by:** DBT semantic translator, DBI SpillManager and liveness
 
 ISA-independent register-file model. `RegisterRef` is `(RegClass, uint16_t index, uint8_t width)` measured in 32-bit lanes. `RegisterSet` is three disjoint bitsets (SGPR / VGPR / ACC_VGPR) sized to the union of CDNA and RDNA hardware bounds (`REGISTER_SET_MAX_*`). For scratch selection across both families, `REGISTER_SET_ALLOCATABLE_SGPRS` gives the conservative `min(CDNA, RDNA)` bound.
 
+`RegisterSet` aliases the header-only `RegisterSetT`, selecting `RegisterSetWordType::Avx2M256` on AVX2 targets and `RegisterSetWordType::StandardUint64` otherwise. The enum selects an internal storage type (`__m256i` or a scalar unsigned integer) without passing vector types as template arguments. The register-set unit tests instantiate both storage types in AVX2 builds so the scalar fallback remains compiled and tested.
+
 `RegisterSet` exposes `expand` / `erase` / `contains` / `none` / `size` / `intersects`, the standard set operators (`|=`, `&=`, `-=`), and a `for_each` visitor that yields tracked single-lane `RegisterRef`s in (SGPR, VGPR, AccVGPR) ascending-index order.
 
 ---

emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/analysis/waitcheck/state.cpp

@@ -52,8 +52,9 @@ bool WaitcheckStateOps::register_set_less(const RegisterSet &lhs, const Register
   std::vector<RegisterRef> rhs_regs;
   lhs_regs.reserve(lhs.size());
   rhs_regs.reserve(rhs.size());
-  lhs.for_each([&](RegisterRef ref) { lhs_regs.push_back(ref); });
-  rhs.for_each([&](RegisterRef ref) { rhs_regs.push_back(ref); });
+  // Inline these callbacks to avoid packing RegisterRef through the aggregate ABI.
+  lhs.for_each([&](RegisterRef ref) __attribute__((always_inline)) { lhs_regs.push_back(ref); });
+  rhs.for_each([&](RegisterRef ref) __attribute__((always_inline)) { rhs_regs.push_back(ref); });
   auto less = [](RegisterRef lhs_ref, RegisterRef rhs_ref) {
     return std::make_tuple(static_cast<uint8_t>(lhs_ref.cls), lhs_ref.index, lhs_ref.width) <
            std::make_tuple(static_cast<uint8_t>(rhs_ref.cls), rhs_ref.index, rhs_ref.width);

emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/analysis/waitcheck/stream.cpp

@@ -23,7 +23,8 @@ bool has_committed_generations(rj_code_arch_t arch) {
 
 std::optional<RegisterRef> first_intersection(const RegisterSet &a, const RegisterSet &b) {
   std::optional<RegisterRef> first;
-  (a & b).for_each([&](RegisterRef ref) {
+  // Keep the optional assignment together with RegisterRef construction.
+  (a & b).for_each([&](RegisterRef ref) __attribute__((always_inline)) {
     if (!first)
       first = ref;
   });

emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/CMakeLists.txt

@@ -5,7 +5,6 @@ rj_add_object_library(rocjitsu_isa
     decoder.cpp
     execution_backend.cpp
     operand.cpp
-    register_set.cpp
     rj_decode.cpp
     target_registry.cpp
 )