[newling]

Motivation

rocJITsu currently lets lane-swap instructions overwrite inactive lanes. This corrupts address calculations in some hipBLASLt kernels and causes numerical failures during emulation.

In a wave64, each vector register holds 64 separate 32-bit values, one per lane. With all lanes enabled, v_permlane16_swap_b32_e32 v0, v1 exchanges these groups:

v1 lanes  0–15  ↔  v0 lanes 16–31
v1 lanes 32–47  ↔  v0 lanes 48–63

The lanes pair up in order: v1[0] swaps with v0[16], v1[1] with v0[17], and so on. Both registers are modified; the other halves retain their values. If both operands name the same register, this swaps neighboring 16-lane blocks within that register. The 32-lane variant exchanges v1[0–31] with v0[32–63].

EXEC has one bit per lane and controls which lanes may write results. This gfx950 example disables every lane before the swap:

s_mov_b64 exec, -1                  // Enable all 64 lanes.
v_mov_b32 v0, 1                     // Every lane: v0 = 1.
v_mov_b32 v1, 2                     // Every lane: v1 = 2.

s_mov_b64 exec, 0                   // Disable every lane.
v_permlane16_swap_b32_e32 v0, v1     // Must not write any lane.
s_mov_b64 exec, -1                  // Re-enable lanes for inspection.

Every lane should still have v0=1 and v1=2. Before this fix, the emulator changes v0 to 2 in lanes 16–31 and 48–63, and v1 to 1 in lanes 0–15 and 32–47, despite EXEC=0.

The CDNA4 ISA Reference Guide, 5 August 2025, §6.2.2, p. 33 states: “A thread only writes a result if the associated bit in the EXEC mask is set to 1.” The swap definitions in §12.8, pp. 218–219 and §12.11, pp. 337–338 specify both output writes without an EXEC override. Their pseudocode omits an explicit mask check; destination masking follows the general VALU output rule.

Technical Details

Add two checks in the shared lane-swap generator: each output write requires its destination lane's EXEC bit to be set. Preserve the snapshots of the original values so using the same register for both operands remains correct, and regenerate the affected CDNA4 and CDNA5 execution sources.

This repairs the hipBLASLt cases that exposed the bug: those kernels enable only some lanes while rearranging offsets into shared memory (LDS). The old emulator's swap also changed the disabled lanes' offsets. They now pass numerical validation with their original lane-swap instructions.

This change corrects destination writes. Inactive-source FI/BOUND_CTRL behavior and source-read observations remain unchanged; the regression does not prescribe the value of an active destination whose source peer is inactive.

Issue Tracking

JIRA ID: AIHPBLAS-3605

Test Plan

Check register values and observed writes for both encodings, supported widths, same and distinct register operands, and full, zero and partial EXEC masks. Run the standalone HIP probe, reduced hipBLASLt controls, adjacent native tests, generator tests and changed-file hooks.

Test Result

The standalone probe improves from 384 mismatched lane records out of 768 to zero. All 11 previously failing reduced hipBLASLt cases and four additional short-tail/edge cases pass. The separate known missing-wait reports remain detectable. Focused native tests, generator tests and hooks pass, with one generator test skipped. Validation used functional emulation; physical gfx950 validation has not been performed.

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/rocm-systems/blob/develop/CONTRIBUTING.md.

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[kuhar]

We should apply the destination EXEC fix to the CDNA4-to-CDNA3 swap lowering too. In emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/dbt/semantic/cdna4_to_cdna3.cpp:767, it still explicitly treats swaps as EXEC-ignoring, and the final moves use full low/high group masks without intersecting saved_exec. For example, an e32 16-lane swap entered with only lane 0 enabled still overwrites inactive destination lane 16 after translation, unlike the corrected interpreter.

Please retain all-lane gathering, intersect each output mask with the saved EXEC, and add a partial-EXEC translation execution regression. BinaryTranslatorE2E.Cdna4ToCdna3Permlane16SwapWritesBothRowPairs currently checks only emitted mask literals, so it passes despite this mismatch.

[newling]

The CDNA4->CDNA3 lowering is a good spot, @kuhar I think it has been fixed in 2ba2585 now.

[kuhar]

LGTM

[systems-assistant]

TheRock Submodule Bump Activity

Newest first

• 2026-10-07 — Included in TheRock via ROCm/TheRock#8809.