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[rocjitsu] Enable functional gfx1251 simulation - #11131
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I think we should build the target/version mismatch cases from an otherwise valid configuration and assert the specific mismatch diagnostic (emulation/rocjitsu/tests/config_test.cpp:1437). At e5d5b748, both fixtures fail first with vm.gpu.device.num_sdma_queues_per_engine must be nonzero when vm.gpu.device.num_sdma_engines is nonzero; matching target/version pairs fail identically. The loader validates the device before checking the target/version, and these fixtures also omit topology. Consequently, the passing EXPECT_THROW assertions do not protect the mismatch guard. Starting from gfx1251_synthetic.json and changing only the target/version pair would avoid these unrelated failures.
Enable simulator execution on the full gfx1251 target provider now that every newly legal instruction has a real callback. Keep the architecture-only CDNA5 default on gfx1250, and keep the model-only provider callback-free by deriving its bindings without execution capability. Use immutable concrete-target capabilities instead of adding a second architecture enum or copying the CDNA5 decoder. gfx1250 and gfx1251 share the CDNA5 encoding and execution infrastructure, while the concrete target feature set continues to decide instruction legality and the setreg behavior difference. Add a deliberately synthetic one-CU gfx1251 functional configuration and a table-driven end-to-end simulator regression for all nine gfx1251 instructions plus a full-dispatch regression for the target-specific setreg behavior. Each case builds a concrete gfx1251 ELF from exact LLVM MC-test instruction bytes, loads it through normal config, submits it through the AQL queue, executes through the command processor and compute unit, stores exact results to simulated memory, and checks dispatch count, queue advancement, completion, mnemonic execution count, and all 32 lanes. The shift-left-add oracle uses only the documented 0-through-4 shift range. Target/version mismatches remain fail-closed. Update the Sphinx architecture and supported-target pages so they no longer describe gfx1251 as decode-only. Document that its checked-in topology is a synthetic functional configuration rather than a product or timing model. The encodings remain traceable to the checked-in CDNA5 XML and provenance manifest, llvm/lib/Target/AMDGPU/VOP3PInstructions.td, and gfx1251 MC tests. No generated ISA or DBT output changes. This establishes functional simulator execution, not physical gfx1251 validation or cycle/timing fidelity. The WMMA end-to-end case deliberately uses uniform inputs, so it validates dispatch and arithmetic without independently validating lane or element placement. The source-derived WMMA mapping, fixed FP-mode policy, and setreg behavior have repository regression coverage but no gfx1251 hardware differential evidence. Signed-off-by: hanhanW <hanhan0912@gmail.com>
Compile gfx1251 vector-add and matrix-multiply fixtures and run them through the functional simulator. Decode every emitted instruction before dispatch, require execution callbacks, and verify queue completion and output behavior. Give the standalone topology the two wave slots required by a 64-thread wave32 workgroup, and include gfx1251 in generic executable-target coverage. Keep older toolchains buildable while reporting unavailable compiler fixtures as an explicit skipped test.
Bound compiled-kernel preflight decoding to exact sized STT_FUNC ranges and traverse only code reachable from the selected kernel. This prevents inter-function alignment padding and unrelated functions from blocking dispatch while retaining callback validation for the kernel and its callees. Route synthetic configs through the installed-test path lookup and build target/version mismatch cases from valid configurations with an exact diagnostic assertion. Add a symbol-range regression that preserves gaps between function bodies. Signed-off-by: hanhanW <hanhan0912@gmail.com>
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Copilot review overview
🔵 Needs a closer look
The broad simulator, target, ELF, and regression changes warrant final human review.
Review effort: Lite
Findings: None
What changed in this PR
Enables functional gfx1251 simulation using existing CDNA5 infrastructure, with synthetic configuration and end-to-end regressions.
Changes:
- Enables gfx1251 execution capabilities and target validation.
- Adds instruction, setreg, and compiled-kernel simulator tests.
- Adds sized function-range discovery and documentation updates.
| File | Description |
|---|---|
emulation/rocjitsu/tests/kernels/CMakeLists.txt |
Adds gfx1251 kernel fixtures. |
emulation/rocjitsu/tests/isa_target_registry_test.cpp |
Validates executable gfx1251 registration. |
emulation/rocjitsu/tests/gfx1251_compiled_kernel_test.cpp |
Tests compiled-kernel dispatch. |
emulation/rocjitsu/tests/config_test.cpp |
Tests configuration and version validation. |
emulation/rocjitsu/tests/code/relocation_function_table_test.cpp |
Tests function-range gaps. |
emulation/rocjitsu/tests/CMakeLists.txt |
Registers new tests and definitions. |
emulation/rocjitsu/tests/cdna5_gfx1251_simulation_test.cpp |
Adds end-to-end gfx1251 regressions. |
emulation/rocjitsu/tests/cdna5_architecture_test.cpp |
Updates execution expectations. |
emulation/rocjitsu/tests/amdgpu_vm_test.cpp |
Accepts executable concrete targets. |
emulation/rocjitsu/tests/amdgpu_elf_test_support.h |
Declares ELF fixture helpers. |
emulation/rocjitsu/tests/amdgpu_elf_test_support.cpp |
Implements ELF fixture helpers. |
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/isa/arch/amdgpu/cdna5/target_descriptor.h |
Enables gfx1251 execution. |
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.h |
Adds sized function-range APIs. |
emulation/rocjitsu/lib/rocjitsu/src/rocjitsu/code/relocation_function_table.cpp |
Implements function-range discovery. |
emulation/rocjitsu/docs/sphinx/reference/supported-architectures.md |
Documents supported targets. |
emulation/rocjitsu/docs/sphinx/conceptual/architecture.md |
Documents execution and model separation. |
emulation/rocjitsu/docs/configuration.md |
Documents target selection and synthetic configuration. |
emulation/rocjitsu/configs/gfx1251_synthetic.json |
Defines the synthetic gfx1251 topology. |
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Reviewed f09174f; no actionable findings remain. The earlier compiled-kernel preflight, config-path override, and target/version mismatch test concerns are addressed.
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Enable simulator execution on the full gfx1251 target provider now that every newly legal instruction has a real callback. Keep the architecture-only CDNA5 default on gfx1250, and keep the model-only provider callback-free by deriving its bindings without execution capability. Use immutable concrete-target capabilities instead of adding a second architecture enum or copying the CDNA5 decoder. gfx1250 and gfx1251 share the CDNA5 encoding and execution infrastructure, while the concrete target feature set continues to decide instruction legality and the setreg behavior difference. Add a deliberately synthetic one-CU gfx1251 functional configuration and a table-driven end-to-end simulator regression for all nine public gfx1251 instructions plus a full-dispatch regression for the target-specific setreg behavior. Each case builds a concrete gfx1251 ELF from exact public LLVM instruction bytes, loads it through normal config, submits it through the AQL queue, executes through the command processor and compute unit, stores exact results to simulated memory, and checks dispatch count, queue advancement, completion, mnemonic execution count, and all 32 lanes. The shift-left-add oracle uses only the public 0-through-4 shift range. Target/version mismatches remain fail-closed. The encodings remain traceable to the checked-in public CDNA5 XML, repository provenance manifest, llvm/lib/Target/AMDGPU/VOP3PInstructions.td, and public gfx1251 MC tests. No generated ISA or DBT output changes. This establishes functional simulator execution, not physical gfx1251 validation or cycle/timing fidelity. WMMA mapping, FP-mode corners, and setreg hazard behavior have public-source semantic tests but no gfx1251 hardware differential evidence. --------- Signed-off-by: hanhanW <hanhan0912@gmail.com>
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Enable simulator execution on the full gfx1251 target provider now that every newly legal instruction has a real callback. Keep the architecture-only CDNA5 default on gfx1250, and keep the model-only provider callback-free by deriving its bindings without execution capability. Use immutable concrete-target capabilities instead of adding a second architecture enum or copying the CDNA5 decoder. gfx1250 and gfx1251 share the CDNA5 encoding and execution infrastructure, while the concrete target feature set continues to decide instruction legality and the setreg behavior difference. Add a deliberately synthetic one-CU gfx1251 functional configuration and a table-driven end-to-end simulator regression for all nine public gfx1251 instructions plus a full-dispatch regression for the target-specific setreg behavior. Each case builds a concrete gfx1251 ELF from exact public LLVM instruction bytes, loads it through normal config, submits it through the AQL queue, executes through the command processor and compute unit, stores exact results to simulated memory, and checks dispatch count, queue advancement, completion, mnemonic execution count, and all 32 lanes. The shift-left-add oracle uses only the public 0-through-4 shift range. Target/version mismatches remain fail-closed. The encodings remain traceable to the checked-in public CDNA5 XML, repository provenance manifest, llvm/lib/Target/AMDGPU/VOP3PInstructions.td, and public gfx1251 MC tests. No generated ISA or DBT output changes. This establishes functional simulator execution, not physical gfx1251 validation or cycle/timing fidelity. WMMA mapping, FP-mode corners, and setreg hazard behavior have public-source semantic tests but no gfx1251 hardware differential evidence. --------- Signed-off-by: hanhanW <hanhan0912@gmail.com>
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Enable simulator execution on the full gfx1251 target provider now that every newly legal instruction has a real callback. Keep the architecture-only CDNA5 default on gfx1250, and keep the model-only provider callback-free by deriving its bindings without execution capability.
Use immutable concrete-target capabilities instead of adding a second architecture enum or copying the CDNA5 decoder. gfx1250 and gfx1251 share the CDNA5 encoding and execution infrastructure, while the concrete target feature set continues to decide instruction legality and the setreg behavior difference.
Add a deliberately synthetic one-CU gfx1251 functional configuration and a table-driven end-to-end simulator regression for all nine public gfx1251 instructions plus a full-dispatch regression for the target-specific setreg behavior. Each case builds a concrete gfx1251 ELF from exact public LLVM instruction bytes, loads it through normal config, submits it through the AQL queue, executes through the command processor and compute unit, stores exact results to simulated memory, and checks dispatch count, queue advancement, completion, mnemonic execution count, and all 32 lanes. The shift-left-add oracle uses only the public 0-through-4 shift range. Target/version mismatches remain fail-closed.
The encodings remain traceable to the checked-in public CDNA5 XML, repository provenance manifest, llvm/lib/Target/AMDGPU/VOP3PInstructions.td, and public gfx1251 MC tests. No generated ISA or DBT output changes.
This establishes functional simulator execution, not physical gfx1251 validation or cycle/timing fidelity. WMMA mapping, FP-mode corners, and setreg hazard behavior have public-source semantic tests but no gfx1251 hardware differential evidence.