feat(amdsmi): reland gpu_block_t expansion with rdc build fix

projects/amdsmi/CHANGELOG.md

@@ -14,6 +14,10 @@ Full documentation for amd_smi_lib is available at [https://rocm.docs.amd.com/pr
 
 ### Changed
 
+- **Expanded `amdsmi_gpu_block_t` enum with 20 new RAS IP blocks**.  
+  - Added blocks: from `AMDSMI_GPU_BLOCK_MMSCH` to `AMDSMI_GPU_BLOCK_UCIE_PCS` at bit positions 19-38.
+  - Updated `AMDSMI_GPU_BLOCK_LAST` to `AMDSMI_GPU_BLOCK_UCIE_PCS`.
+
 - **An empty nested section now renders as `N/A` in human-readable CLI output**.  
   - Any `amd-smi` command whose output contains an empty sub-section printed a bare `SECTION:` header with nothing under it. It now prints `SECTION: N/A`, matching how empty lists are already rendered.
   - This covers every subcommand that uses the standard human-readable renderer, not only the AI-NIC `RDMA_DEVICES` case that prompted it.
@@ -23,6 +27,9 @@ Full documentation for amd_smi_lib is available at [https://rocm.docs.amd.com/pr
 
 ### Resolved Issues
 
+- **Fixed an out-of-bounds read in the DRM example's RAS block listing**.  
+  - `amd_smi_drm_example.cc` iterated every `amdsmi_gpu_block_t` value but indexed a 14-entry name array, so every block from `AMDSMI_GPU_BLOCK_MCA` onward read past the end of the array and printed a garbage label. The list now covers all 39 blocks and the lookup is bounds-checked.
+
 - **Fixed `amd-smi ras --afid --folder --json` emitting nothing when no CPER files are readable**.  
   - When every `.cper` file in the folder was skipped (e.g. rejected as a symlink), the JSON path printed empty output, so consumers feeding stdout to `json.loads` failed with `Expecting value: line 1 column 1 (char 0)`. It now emits `[]` for that case, matching the `--cper --json` contract.
 

projects/amdsmi/example/amd_smi_drm_example.cc

@@ -1367,12 +1367,17 @@ int main() {
       printf("\tGPU PLX temp measurement: %ld\n\n", temp_measurements[AMDSMI_TEMPERATURE_TYPE_PLX]);
 
       // Get RAS features enabled
-      char block_names[14][10] = {"UMC",       "SDMA", "GFX", "MMHUB", "ATHUB", "PCIE_BIF", "HDP",
-                                  "XGMI_WAFL", "DF",   "SMN", "SEM",   "MP0",   "MP1",      "FUSE"};
+      const char* block_names[] = {
+          "UMC",        "SDMA",     "GFX",   "MMHUB",  "ATHUB", "PCIE_BIF", "HDP",     "XGMI_WAFL",
+          "DF",         "SMN",      "SEM",   "MP0",    "MP1",   "FUSE",     "MCA",     "VCN",
+          "JPEG",       "IH",       "MPIO",  "MMSCH",  "MP5",   "ATU",      "DACC_BE", "ECLR",
+          "KPX_SERDES", "LSDMA",    "MPART", "MPIFOE", "MPRAS", "NBIF",     "NBIO",    "OXRP",
+          "PCIE_PL",    "PCS_XGMI", "PIE",   "CS",     "SHUB",  "SSBDCI",   "UCIE_PCS"};
+      const size_t num_block_names = sizeof(block_names) / sizeof(block_names[0]);
       char status_names[7][10] = {"NONE",    "DISABLED", "PARITY", "SING_C",
                                   "MULT_UC", "POISON",   "ENABLED"};
       amdsmi_ras_err_state_t state = {};
-      int index = 0;
+      size_t index = 0;
       printf("    Output of amdsmi_get_gpu_ras_block_features_enabled:\n");
       for (auto block = AMDSMI_GPU_BLOCK_FIRST; block <= AMDSMI_GPU_BLOCK_LAST;
            block = (amdsmi_gpu_block_t)(block * 2)) {
@@ -1382,7 +1387,8 @@ int main() {
           CHK_AMDSMI_RET(ret)
         }
 
-        printf("\tBlock: %s\n", block_names[index]);
+        // Keeps the lookup in bounds if amdsmi_gpu_block_t gains blocks before this list does.
+        printf("\tBlock: %s\n", index < num_block_names ? block_names[index] : "UNKNOWN");
         printf("\tStatus: %s\n", status_names[state]);
         index++;
       }

projects/amdsmi/include/amd_smi/amdsmi.h

@@ -1773,7 +1773,27 @@ typedef enum {
   AMDSMI_GPU_BLOCK_JPEG = (1ULL << 16),           //!< JPEG block
   AMDSMI_GPU_BLOCK_IH = (1ULL << 17),             //!< IH block
   AMDSMI_GPU_BLOCK_MPIO = (1ULL << 18),           //!< MPIO block
-  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_MPIO,
+  AMDSMI_GPU_BLOCK_MMSCH = (1ULL << 19),          //!< MMSCH block
+  AMDSMI_GPU_BLOCK_MP5 = (1ULL << 20),            //!< MP5 block
+  AMDSMI_GPU_BLOCK_ATU = (1ULL << 21),            //!< ATU block
+  AMDSMI_GPU_BLOCK_DACC_BE = (1ULL << 22),        //!< DACC_BE block
+  AMDSMI_GPU_BLOCK_ECLR = (1ULL << 23),           //!< ECLR block
+  AMDSMI_GPU_BLOCK_KPX_SERDES = (1ULL << 24),     //!< KPX_SERDES block
+  AMDSMI_GPU_BLOCK_LSDMA = (1ULL << 25),          //!< LSDMA block
+  AMDSMI_GPU_BLOCK_MPART = (1ULL << 26),          //!< MPART block
+  AMDSMI_GPU_BLOCK_MPIFOE = (1ULL << 27),         //!< MPIFOE block
+  AMDSMI_GPU_BLOCK_MPRAS = (1ULL << 28),          //!< MPRAS block
+  AMDSMI_GPU_BLOCK_NBIF = (1ULL << 29),           //!< NBIF block
+  AMDSMI_GPU_BLOCK_NBIO = (1ULL << 30),           //!< NBIO block
+  AMDSMI_GPU_BLOCK_OXRP = (1ULL << 31),           //!< OXRP block
+  AMDSMI_GPU_BLOCK_PCIE_PL = (1ULL << 32),        //!< PCIE_PL block
+  AMDSMI_GPU_BLOCK_PCS_XGMI = (1ULL << 33),       //!< PCS_XGMI block
+  AMDSMI_GPU_BLOCK_PIE = (1ULL << 34),            //!< PIE block
+  AMDSMI_GPU_BLOCK_CS = (1ULL << 35),             //!< CS block
+  AMDSMI_GPU_BLOCK_SHUB = (1ULL << 36),           //!< SHUB block
+  AMDSMI_GPU_BLOCK_SSBDCI = (1ULL << 37),         //!< SSBDCI block
+  AMDSMI_GPU_BLOCK_UCIE_PCS = (1ULL << 38),       //!< UCIE_PCS block
+  AMDSMI_GPU_BLOCK_LAST = AMDSMI_GPU_BLOCK_UCIE_PCS,
   AMDSMI_GPU_BLOCK_RESERVED = (1ULL << 63)
 } amdsmi_gpu_block_t;
 

projects/amdsmi/py-interface/amdsmi_interface.py

@@ -612,6 +612,26 @@ class AmdSmiGpuBlock(IntEnum):
     JPEG = amdsmi_wrapper.AMDSMI_GPU_BLOCK_JPEG
     IH = amdsmi_wrapper.AMDSMI_GPU_BLOCK_IH
     MPIO = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MPIO
+    MMSCH = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MMSCH
+    MP5 = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MP5
+    ATU = amdsmi_wrapper.AMDSMI_GPU_BLOCK_ATU
+    DACC_BE = amdsmi_wrapper.AMDSMI_GPU_BLOCK_DACC_BE
+    ECLR = amdsmi_wrapper.AMDSMI_GPU_BLOCK_ECLR
+    KPX_SERDES = amdsmi_wrapper.AMDSMI_GPU_BLOCK_KPX_SERDES
+    LSDMA = amdsmi_wrapper.AMDSMI_GPU_BLOCK_LSDMA
+    MPART = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MPART
+    MPIFOE = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MPIFOE
+    MPRAS = amdsmi_wrapper.AMDSMI_GPU_BLOCK_MPRAS
+    NBIF = amdsmi_wrapper.AMDSMI_GPU_BLOCK_NBIF
+    NBIO = amdsmi_wrapper.AMDSMI_GPU_BLOCK_NBIO
+    OXRP = amdsmi_wrapper.AMDSMI_GPU_BLOCK_OXRP
+    PCIE_PL = amdsmi_wrapper.AMDSMI_GPU_BLOCK_PCIE_PL
+    PCS_XGMI = amdsmi_wrapper.AMDSMI_GPU_BLOCK_PCS_XGMI
+    PIE = amdsmi_wrapper.AMDSMI_GPU_BLOCK_PIE
+    CS = amdsmi_wrapper.AMDSMI_GPU_BLOCK_CS
+    SHUB = amdsmi_wrapper.AMDSMI_GPU_BLOCK_SHUB
+    SSBDCI = amdsmi_wrapper.AMDSMI_GPU_BLOCK_SSBDCI
+    UCIE_PCS = amdsmi_wrapper.AMDSMI_GPU_BLOCK_UCIE_PCS
     RESERVED = amdsmi_wrapper.AMDSMI_GPU_BLOCK_RESERVED
 
 
@@ -3656,7 +3676,7 @@ def amdsmi_get_gpu_ras_block_features_enabled(
             continue
         gpu_block_name = gpu_block.name
         if gpu_block.name == "LAST":
-            gpu_block_name = "MPIO"
+            gpu_block_name = "UCIE_PCS"
         _check_res(
             amdsmi_wrapper.amdsmi_get_gpu_ras_block_features_enabled(
                 processor_handle,

projects/amdsmi/py-interface/amdsmi_wrapper.py

@@ -1963,7 +1963,27 @@ class struct_amdsmi_evt_notification_data_t(Structure):
     65536: 'AMDSMI_GPU_BLOCK_JPEG',
     131072: 'AMDSMI_GPU_BLOCK_IH',
     262144: 'AMDSMI_GPU_BLOCK_MPIO',
-    262144: 'AMDSMI_GPU_BLOCK_LAST',
+    524288: 'AMDSMI_GPU_BLOCK_MMSCH',
+    1048576: 'AMDSMI_GPU_BLOCK_MP5',
+    2097152: 'AMDSMI_GPU_BLOCK_ATU',
+    4194304: 'AMDSMI_GPU_BLOCK_DACC_BE',
+    8388608: 'AMDSMI_GPU_BLOCK_ECLR',
+    16777216: 'AMDSMI_GPU_BLOCK_KPX_SERDES',
+    33554432: 'AMDSMI_GPU_BLOCK_LSDMA',
+    67108864: 'AMDSMI_GPU_BLOCK_MPART',
+    134217728: 'AMDSMI_GPU_BLOCK_MPIFOE',
+    268435456: 'AMDSMI_GPU_BLOCK_MPRAS',
+    536870912: 'AMDSMI_GPU_BLOCK_NBIF',
+    1073741824: 'AMDSMI_GPU_BLOCK_NBIO',
+    2147483648: 'AMDSMI_GPU_BLOCK_OXRP',
+    4294967296: 'AMDSMI_GPU_BLOCK_PCIE_PL',
+    8589934592: 'AMDSMI_GPU_BLOCK_PCS_XGMI',
+    17179869184: 'AMDSMI_GPU_BLOCK_PIE',
+    34359738368: 'AMDSMI_GPU_BLOCK_CS',
+    68719476736: 'AMDSMI_GPU_BLOCK_SHUB',
+    137438953472: 'AMDSMI_GPU_BLOCK_SSBDCI',
+    274877906944: 'AMDSMI_GPU_BLOCK_UCIE_PCS',
+    274877906944: 'AMDSMI_GPU_BLOCK_LAST',
     9223372036854775808: 'AMDSMI_GPU_BLOCK_RESERVED',
 }
 AMDSMI_GPU_BLOCK_INVALID = 0
@@ -1987,7 +2007,27 @@ class struct_amdsmi_evt_notification_data_t(Structure):
 AMDSMI_GPU_BLOCK_JPEG = 65536
 AMDSMI_GPU_BLOCK_IH = 131072
 AMDSMI_GPU_BLOCK_MPIO = 262144
-AMDSMI_GPU_BLOCK_LAST = 262144
+AMDSMI_GPU_BLOCK_MMSCH = 524288
+AMDSMI_GPU_BLOCK_MP5 = 1048576
+AMDSMI_GPU_BLOCK_ATU = 2097152
+AMDSMI_GPU_BLOCK_DACC_BE = 4194304
+AMDSMI_GPU_BLOCK_ECLR = 8388608
+AMDSMI_GPU_BLOCK_KPX_SERDES = 16777216
+AMDSMI_GPU_BLOCK_LSDMA = 33554432
+AMDSMI_GPU_BLOCK_MPART = 67108864
+AMDSMI_GPU_BLOCK_MPIFOE = 134217728
+AMDSMI_GPU_BLOCK_MPRAS = 268435456
+AMDSMI_GPU_BLOCK_NBIF = 536870912
+AMDSMI_GPU_BLOCK_NBIO = 1073741824
+AMDSMI_GPU_BLOCK_OXRP = 2147483648
+AMDSMI_GPU_BLOCK_PCIE_PL = 4294967296
+AMDSMI_GPU_BLOCK_PCS_XGMI = 8589934592
+AMDSMI_GPU_BLOCK_PIE = 17179869184
+AMDSMI_GPU_BLOCK_CS = 34359738368
+AMDSMI_GPU_BLOCK_SHUB = 68719476736
+AMDSMI_GPU_BLOCK_SSBDCI = 137438953472
+AMDSMI_GPU_BLOCK_UCIE_PCS = 274877906944
+AMDSMI_GPU_BLOCK_LAST = 274877906944
 AMDSMI_GPU_BLOCK_RESERVED = 9223372036854775808
 amdsmi_gpu_block_t = ctypes.c_uint64 # enum
 
@@ -5082,16 +5122,26 @@ class struct_amdsmi_ttm_info_t(Structure):
     'AMDSMI_FW_ID_SEC_POLICY_STAGE2', 'AMDSMI_FW_ID_SMU',
     'AMDSMI_FW_ID_TA_RAS', 'AMDSMI_FW_ID_TA_XGMI', 'AMDSMI_FW_ID_UVD',
     'AMDSMI_FW_ID_VCE', 'AMDSMI_FW_ID_VCN', 'AMDSMI_FW_ID__MAX',
-    'AMDSMI_GPU_BLOCK_ATHUB', 'AMDSMI_GPU_BLOCK_DF',
+    'AMDSMI_GPU_BLOCK_ATHUB', 'AMDSMI_GPU_BLOCK_ATU',
+    'AMDSMI_GPU_BLOCK_CS', 'AMDSMI_GPU_BLOCK_DACC_BE',
+    'AMDSMI_GPU_BLOCK_DF', 'AMDSMI_GPU_BLOCK_ECLR',
     'AMDSMI_GPU_BLOCK_FIRST', 'AMDSMI_GPU_BLOCK_FUSE',
     'AMDSMI_GPU_BLOCK_GFX', 'AMDSMI_GPU_BLOCK_HDP',
     'AMDSMI_GPU_BLOCK_IH', 'AMDSMI_GPU_BLOCK_INVALID',
-    'AMDSMI_GPU_BLOCK_JPEG', 'AMDSMI_GPU_BLOCK_LAST',
+    'AMDSMI_GPU_BLOCK_JPEG', 'AMDSMI_GPU_BLOCK_KPX_SERDES',
+    'AMDSMI_GPU_BLOCK_LAST', 'AMDSMI_GPU_BLOCK_LSDMA',
     'AMDSMI_GPU_BLOCK_MCA', 'AMDSMI_GPU_BLOCK_MMHUB',
-    'AMDSMI_GPU_BLOCK_MP0', 'AMDSMI_GPU_BLOCK_MP1',
-    'AMDSMI_GPU_BLOCK_MPIO', 'AMDSMI_GPU_BLOCK_PCIE_BIF',
-    'AMDSMI_GPU_BLOCK_RESERVED', 'AMDSMI_GPU_BLOCK_SDMA',
-    'AMDSMI_GPU_BLOCK_SEM', 'AMDSMI_GPU_BLOCK_SMN',
+    'AMDSMI_GPU_BLOCK_MMSCH', 'AMDSMI_GPU_BLOCK_MP0',
+    'AMDSMI_GPU_BLOCK_MP1', 'AMDSMI_GPU_BLOCK_MP5',
+    'AMDSMI_GPU_BLOCK_MPART', 'AMDSMI_GPU_BLOCK_MPIFOE',
+    'AMDSMI_GPU_BLOCK_MPIO', 'AMDSMI_GPU_BLOCK_MPRAS',
+    'AMDSMI_GPU_BLOCK_NBIF', 'AMDSMI_GPU_BLOCK_NBIO',
+    'AMDSMI_GPU_BLOCK_OXRP', 'AMDSMI_GPU_BLOCK_PCIE_BIF',
+    'AMDSMI_GPU_BLOCK_PCIE_PL', 'AMDSMI_GPU_BLOCK_PCS_XGMI',
+    'AMDSMI_GPU_BLOCK_PIE', 'AMDSMI_GPU_BLOCK_RESERVED',
+    'AMDSMI_GPU_BLOCK_SDMA', 'AMDSMI_GPU_BLOCK_SEM',
+    'AMDSMI_GPU_BLOCK_SHUB', 'AMDSMI_GPU_BLOCK_SMN',
+    'AMDSMI_GPU_BLOCK_SSBDCI', 'AMDSMI_GPU_BLOCK_UCIE_PCS',
     'AMDSMI_GPU_BLOCK_UMC', 'AMDSMI_GPU_BLOCK_VCN',
     'AMDSMI_GPU_BLOCK_XGMI_WAFL', 'AMDSMI_INIT_ALL_PROCESSORS',
     'AMDSMI_INIT_AMD_APUS', 'AMDSMI_INIT_AMD_CPUS',

projects/amdsmi/rust-interface/src/amdsmi_wrapper.rs

@@ -2213,7 +2213,7 @@ impl AmdsmiGpuBlockT {
     pub const AmdsmiGpuBlockUmc: AmdsmiGpuBlockT = AmdsmiGpuBlockT::AmdsmiGpuBlockFirst;
 }
 impl AmdsmiGpuBlockT {
-    pub const AmdsmiGpuBlockLast: AmdsmiGpuBlockT = AmdsmiGpuBlockT::AmdsmiGpuBlockMpio;
+    pub const AmdsmiGpuBlockLast: AmdsmiGpuBlockT = AmdsmiGpuBlockT::AmdsmiGpuBlockUciePcs;
 }
 #[repr(u64)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -2238,6 +2238,26 @@ pub enum AmdsmiGpuBlockT {
     AmdsmiGpuBlockJpeg = 65536,
     AmdsmiGpuBlockIh = 131072,
     AmdsmiGpuBlockMpio = 262144,
+    AmdsmiGpuBlockMmsch = 524288,
+    AmdsmiGpuBlockMp5 = 1048576,
+    AmdsmiGpuBlockAtu = 2097152,
+    AmdsmiGpuBlockDaccBe = 4194304,
+    AmdsmiGpuBlockEclr = 8388608,
+    AmdsmiGpuBlockKpxSerdes = 16777216,
+    AmdsmiGpuBlockLsdma = 33554432,
+    AmdsmiGpuBlockMpart = 67108864,
+    AmdsmiGpuBlockMpifoe = 134217728,
+    AmdsmiGpuBlockMpras = 268435456,
+    AmdsmiGpuBlockNbif = 536870912,
+    AmdsmiGpuBlockNbio = 1073741824,
+    AmdsmiGpuBlockOxrp = 2147483648,
+    AmdsmiGpuBlockPciePl = 4294967296,
+    AmdsmiGpuBlockPcsXgmi = 8589934592,
+    AmdsmiGpuBlockPie = 17179869184,
+    AmdsmiGpuBlockCs = 34359738368,
+    AmdsmiGpuBlockShub = 68719476736,
+    AmdsmiGpuBlockSsbdci = 137438953472,
+    AmdsmiGpuBlockUciePcs = 274877906944,
     AmdsmiGpuBlockReserved = 9223372036854775808,
 }
 impl AmdsmiClkLimitTypeT {

projects/amdsmi/tests/amd_smi_test/functional/gpu/ras/err_cnt_read_test.cc

@@ -81,7 +81,7 @@ void TestErrCntRead::Run(void) {
           std::cout << "Block Error Mask: 0x" << std::hex << enabled_mask << std::endl;
         }
       }
-      for (uint32_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
+      for (uint64_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
         DISPLAY_AMDSMI_API("amdsmi_get_gpu_ecc_status", "gpu=" + std::to_string(i), VERB(STANDARD));
         err = amdsmi_get_gpu_ecc_status(processor_handles_[i], static_cast<amdsmi_gpu_block_t>(b),
                                         &err_state);

projects/amdsmi/tests/amd_smi_test/test_common.cc

@@ -32,18 +32,48 @@ static_assert(AMDSMI_DEV_PERF_LEVEL_LAST == AMDSMI_DEV_PERF_LEVEL_DETERMINISM,
               "kDevPerfLvlNameMap needs to be updated");
 
 static const std::map<amdsmi_gpu_block_t, const char*> kBlockNameMap = {
-    {AMDSMI_GPU_BLOCK_UMC, "UMC"},     {AMDSMI_GPU_BLOCK_SDMA, "SDMA"},
-    {AMDSMI_GPU_BLOCK_GFX, "GFX"},     {AMDSMI_GPU_BLOCK_MMHUB, "MMHUB"},
-    {AMDSMI_GPU_BLOCK_ATHUB, "ATHUB"}, {AMDSMI_GPU_BLOCK_PCIE_BIF, "PCIE_BIF"},
-    {AMDSMI_GPU_BLOCK_HDP, "HDP"},     {AMDSMI_GPU_BLOCK_XGMI_WAFL, "XGMI_WAFL"},
-    {AMDSMI_GPU_BLOCK_DF, "DF"},       {AMDSMI_GPU_BLOCK_SMN, "SMN"},
-    {AMDSMI_GPU_BLOCK_SEM, "SEM"},     {AMDSMI_GPU_BLOCK_MP0, "MP0"},
-    {AMDSMI_GPU_BLOCK_MP1, "MP1"},     {AMDSMI_GPU_BLOCK_FUSE, "FUSE"},
-    {AMDSMI_GPU_BLOCK_MCA, "MCA"},     {AMDSMI_GPU_BLOCK_VCN, "VCN"},
-    {AMDSMI_GPU_BLOCK_JPEG, "JPEG"},   {AMDSMI_GPU_BLOCK_IH, "IH"},
+    {AMDSMI_GPU_BLOCK_UMC, "UMC"},
+    {AMDSMI_GPU_BLOCK_SDMA, "SDMA"},
+    {AMDSMI_GPU_BLOCK_GFX, "GFX"},
+    {AMDSMI_GPU_BLOCK_MMHUB, "MMHUB"},
+    {AMDSMI_GPU_BLOCK_ATHUB, "ATHUB"},
+    {AMDSMI_GPU_BLOCK_PCIE_BIF, "PCIE_BIF"},
+    {AMDSMI_GPU_BLOCK_HDP, "HDP"},
+    {AMDSMI_GPU_BLOCK_XGMI_WAFL, "XGMI_WAFL"},
+    {AMDSMI_GPU_BLOCK_DF, "DF"},
+    {AMDSMI_GPU_BLOCK_SMN, "SMN"},
+    {AMDSMI_GPU_BLOCK_SEM, "SEM"},
+    {AMDSMI_GPU_BLOCK_MP0, "MP0"},
+    {AMDSMI_GPU_BLOCK_MP1, "MP1"},
+    {AMDSMI_GPU_BLOCK_FUSE, "FUSE"},
+    {AMDSMI_GPU_BLOCK_MCA, "MCA"},
+    {AMDSMI_GPU_BLOCK_VCN, "VCN"},
+    {AMDSMI_GPU_BLOCK_JPEG, "JPEG"},
+    {AMDSMI_GPU_BLOCK_IH, "IH"},
     {AMDSMI_GPU_BLOCK_MPIO, "MPIO"},
+    {AMDSMI_GPU_BLOCK_MMSCH, "MMSCH"},
+    {AMDSMI_GPU_BLOCK_MP5, "MP5"},
+    {AMDSMI_GPU_BLOCK_ATU, "ATU"},
+    {AMDSMI_GPU_BLOCK_DACC_BE, "DACC_BE"},
+    {AMDSMI_GPU_BLOCK_ECLR, "ECLR"},
+    {AMDSMI_GPU_BLOCK_KPX_SERDES, "KPX_SERDES"},
+    {AMDSMI_GPU_BLOCK_LSDMA, "LSDMA"},
+    {AMDSMI_GPU_BLOCK_MPART, "MPART"},
+    {AMDSMI_GPU_BLOCK_MPIFOE, "MPIFOE"},
+    {AMDSMI_GPU_BLOCK_MPRAS, "MPRAS"},
+    {AMDSMI_GPU_BLOCK_NBIF, "NBIF"},
+    {AMDSMI_GPU_BLOCK_NBIO, "NBIO"},
+    {AMDSMI_GPU_BLOCK_OXRP, "OXRP"},
+    {AMDSMI_GPU_BLOCK_PCIE_PL, "PCIE_PL"},
+    {AMDSMI_GPU_BLOCK_PCS_XGMI, "PCS_XGMI"},
+    {AMDSMI_GPU_BLOCK_PIE, "PIE"},
+    {AMDSMI_GPU_BLOCK_CS, "CS"},
+    {AMDSMI_GPU_BLOCK_SHUB, "SHUB"},
+    {AMDSMI_GPU_BLOCK_SSBDCI, "SSBDCI"},
+    {AMDSMI_GPU_BLOCK_UCIE_PCS, "UCIE_PCS"},
 };
-static_assert(AMDSMI_GPU_BLOCK_LAST == AMDSMI_GPU_BLOCK_MPIO, "kBlockNameMap needs to be updated");
+static_assert(AMDSMI_GPU_BLOCK_LAST == AMDSMI_GPU_BLOCK_UCIE_PCS,
+              "kBlockNameMap needs to be updated");
 
 static const char* kRasErrStateStrings[] = {
     "None",                     // AMDSMI_RAS_ERR_STATE_NONE

projects/rdc/CHANGELOG.md

@@ -29,8 +29,12 @@ Full documentation for RDC is available at [ROCm DataCenter Tool User Guide](htt
 - Removed RVS integration. [RVS](https://github.com/ROCm/ROCmValidationSuite) is built independently of RDC and TheRock, so its integration has been disabled.
   - `BUILD_RVS` now defaults to `OFF` (#7116).
 
+- Removed the unused `GetBlockNameStr()` test helper and its GPU block name map. Nothing called it, and its `static_assert` on `AMDSMI_GPU_BLOCK_LAST` broke the RDC build whenever AMD SMI added an IP block (#10949).
+
 ### Resolved Issues
 
+- `RDC_FI_ECC_CORRECT_TOTAL`, `RDC_FI_ECC_UNCORRECT_TOTAL`, and `RDC_FI_ECC_DEFERRED_TOTAL` no longer hang when AMD SMI defines GPU blocks above bit 31. The block iteration used a 32-bit counter that wrapped to zero instead of terminating.
+
 - The `Failed to insert module: N3amd3rdc10RdcRVSLibE` error no longer occurs.
 
 ## RDC 1.3.0 for ROCm 7.13.0

projects/rdc/rdc_libs/rdc/src/RdcMetricFetcherImpl.cc

@@ -300,7 +300,8 @@ void RdcMetricFetcherImpl::get_ecc_total(uint32_t gpu_index, rdc_field_t field_i
   if (!value) {
     return;
   }
-  for (uint32_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
+  // amdsmi_gpu_block_t is a 64-bit flag enum; a 32-bit counter wraps to 0 and never exits.
+  for (uint64_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
     err =
         amdsmi_get_gpu_ecc_status(processor_handle, static_cast<amdsmi_gpu_block_t>(b), &err_state);
     if (err != AMDSMI_STATUS_SUCCESS) {
@@ -412,7 +413,8 @@ void RdcMetricFetcherImpl::get_ecc_deferred_total(uint32_t gpu_index, rdc_field_
   amdsmi_status_t err = get_processor_handle_from_id(gpu_index, &processor_handle);
 
   uint64_t deferred_count = 0;
-  for (uint32_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
+  // amdsmi_gpu_block_t is a 64-bit flag enum; a 32-bit counter wraps to 0 and never exits.
+  for (uint64_t b = AMDSMI_GPU_BLOCK_FIRST; b <= AMDSMI_GPU_BLOCK_LAST; b = b * 2) {
     amdsmi_ras_err_state_t err_state = AMDSMI_RAS_ERR_STATE_INVALID;
     err =
         amdsmi_get_gpu_ecc_status(processor_handle, static_cast<amdsmi_gpu_block_t>(b), &err_state);

projects/rdc/tests/rdc_tests/test_common.cc

@@ -47,20 +47,6 @@ THE SOFTWARE.
     },
 };
 */
-static const std::map<amdsmi_gpu_block_t, const char*> kBlockNameMap = {
-    {AMDSMI_GPU_BLOCK_UMC, "UMC"},     {AMDSMI_GPU_BLOCK_SDMA, "SDMA"},
-    {AMDSMI_GPU_BLOCK_GFX, "GFX"},     {AMDSMI_GPU_BLOCK_MMHUB, "MMHUB"},
-    {AMDSMI_GPU_BLOCK_ATHUB, "ATHUB"}, {AMDSMI_GPU_BLOCK_PCIE_BIF, "PCIE_BIF"},
-    {AMDSMI_GPU_BLOCK_HDP, "HDP"},     {AMDSMI_GPU_BLOCK_XGMI_WAFL, "XGMI_WAFL"},
-    {AMDSMI_GPU_BLOCK_DF, "DF"},       {AMDSMI_GPU_BLOCK_SMN, "SMN"},
-    {AMDSMI_GPU_BLOCK_SEM, "SEM"},     {AMDSMI_GPU_BLOCK_MP0, "MP0"},
-    {AMDSMI_GPU_BLOCK_MP1, "MP1"},     {AMDSMI_GPU_BLOCK_FUSE, "FUSE"},
-    {AMDSMI_GPU_BLOCK_MCA, "MCA"},     {AMDSMI_GPU_BLOCK_VCN, "VCN"},
-    {AMDSMI_GPU_BLOCK_JPEG, "JPEG"},   {AMDSMI_GPU_BLOCK_IH, "IH"},
-    {AMDSMI_GPU_BLOCK_MPIO, "MPIO"},
-};
-static_assert(AMDSMI_GPU_BLOCK_LAST == AMDSMI_GPU_BLOCK_MPIO, "kBlockNameMap needs to be updated");
-
 static const char* kRasErrStateStrings[] = {
     "None",                     // AMDSMI_RAS_ERR_STATE_NONE
     "Disabled",                 // AMDSMI_RAS_ERR_STATE_DISABLED
@@ -209,7 +195,6 @@ uint32_t ProcessCmdline(RDCTstGlobals* test, int arg_cnt, char** arg_list) {
   return 1;
 }
 
-const char* GetBlockNameStr(amdsmi_gpu_block_t id) { return kBlockNameMap.at(id); }
 const char* GetErrStateNameStr(amdsmi_ras_err_state_t st) { return kErrStateNameMap.at(st); }
 /*const char *GetGRPCChanStateStr(grpc_connectivity_state st) {
   return kGRPCChanState.at(st);

projects/rdc/tests/rdc_tests/test_common.h

@@ -45,7 +45,6 @@ struct RDCTstGlobals {
 uint32_t ProcessCmdline(RDCTstGlobals* test, int arg_cnt, char** arg_list);
 
 void PrintTestHeader(uint32_t dv_ind);
-const char* GetBlockNameStr(amdsmi_gpu_block_t id);
 const char* GetErrStateNameStr(amdsmi_ras_err_state_t st);
 // const char *GetGRPCChanStateStr(grpc_connectivity_state st);
 const char* FreqEnumToStr(amdsmi_clk_type_t rsmi_clk);