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[hipblaslt] Enable MXFP4 + DtlPlusLdsBuf #5251

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Merged
nakajee merged 1 commit into from
Mar 10, 2026
Merged

[hipblaslt] Enable MXFP4 + DtlPlusLdsBuf #5251

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4 changes: 4 additions & 0 deletions projects/hipblaslt/tensilelite/Tensile/Components/StreamK.py
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Original file line number Diff line number Diff line change
Expand Up @@ -124,7 +124,11 @@ def skTileIndex(self, writer, kernel, sTmp, tPA, tPB):
# Always reset pointers to handle odd-exit case which moves LRO to the upper bank
if kernel["PrefetchGlobalRead"]: # not self.prefetchAcrossPersistent
module.add(writer.localReadResetOffsets(kernel, tPA))
if kernel["ProblemType"]["MXBlockA"]:
module.add(writer.localReadResetOffsets(kernel, tPA["MX"]))
module.add(writer.localReadResetOffsets(kernel, tPB))
if kernel["ProblemType"]["MXBlockB"]:
module.add(writer.localReadResetOffsets(kernel, tPB["MX"]))

module.addComment0("StreamK calculate tile idx and map to WG")

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6 changes: 6 additions & 0 deletions projects/hipblaslt/tensilelite/Tensile/KernelWriter.py
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Expand Up @@ -5919,8 +5919,14 @@ def GNLCOInit(tc):
# Need backup for the first LocalReadAddr only (others will be calculated from the first one)
self.states.a.startVgprLocalReadAddrOrig = vgprIdx
vgprIdx += 1 if self.states.a.numVgprLocalReadAddr > 0 else 0
if kernel["ProblemType"]["MXBlockA"]:
self.states.mxsa.startVgprLocalReadAddrOrig = vgprIdx
vgprIdx += 1 if self.states.mxsa.numVgprLocalReadAddr > 0 else 0
self.states.b.startVgprLocalReadAddrOrig = vgprIdx
vgprIdx += 1 if self.states.b.numVgprLocalReadAddr > 0 else 0
if kernel["ProblemType"]["MXBlockB"]:
self.states.mxsb.startVgprLocalReadAddrOrig = vgprIdx
vgprIdx += 1 if self.states.mxsb.numVgprLocalReadAddr > 0 else 0

# ----------------------------
# TODO: alignment hack, figure out a better solution
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8 changes: 8 additions & 0 deletions projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py
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Expand Up @@ -1156,9 +1156,17 @@ def macroAndSet(self, kernel, tPA, tPB) -> Module:
if self.states.a.numVgprLocalReadAddr > 0:
module.add(RegSet("v", "vgprLocalReadAddrOrigA", \
self.states.a.startVgprLocalReadAddrOrig))
if kernel["ProblemType"]["MXBlockA"]:
if self.states.mxsa.numVgprLocalReadAddr > 0:
module.add(RegSet("v", "vgprLocalReadAddrOrigMXSA", \
self.states.mxsa.startVgprLocalReadAddrOrig))
if self.states.b.numVgprLocalReadAddr > 0:
module.add(RegSet("v", "vgprLocalReadAddrOrigB", \
self.states.b.startVgprLocalReadAddrOrig))
if kernel["ProblemType"]["MXBlockB"]:
if self.states.mxsb.numVgprLocalReadAddr > 0:
module.add(RegSet("v", "vgprLocalReadAddrOrigMXSB", \
self.states.mxsb.startVgprLocalReadAddrOrig))
if self.states.m.numVgprLocalReadAddr > 0:
module.add(RegSet("v", "vgprLocalReadAddrMetadata", \
self.states.m.startVgprLocalReadAddr))
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