codegen: handle unaligned K for TN#3679
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b-shi
reviewed
Jan 9, 2026
aazz44ss
reviewed
Jan 12, 2026
…interleave cannot be enabled
- require tiles1 = SizeJ / MT1 to be an integer (SizeJ % MT1 == 0)
# - require lowbit(tiles1) > 1 so that G=min(lowbit(tiles1), LVCB) is > 1 (enabled)
# Note: if lowbit(tiles1) == 1, then G==1 and the kernel disables BAddrInterleave.
aazz44ss
reviewed
Jan 14, 2026
aazz44ss
reviewed
Jan 14, 2026
Add a VS Code/Cursor extension to hover Tensile YAML and view/edit a single kernel block, and ignore VSIX/build artifacts.
This reverts commit 5ad6a9a.
Resolve conflicts in Tensile codegen and gfx950 logic YAML.
perfci run on commit 250655e |
Codecov Report✅ All modified and coverable lines are covered by tests. ❌ Your project status has failed because the head coverage (76.83%) is below the target coverage (80.00%). You can increase the head coverage or adjust the target coverage. Additional details and impacted files@@ Coverage Diff @@
## develop #3679 +/- ##
========================================
Coverage 65.33% 65.33%
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Files 1579 1577 -2
Lines 242119 242154 +35
Branches 33920 33912 -8
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+ Hits 158167 158201 +34
- Misses 69931 69945 +14
+ Partials 14021 14008 -13
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perfci run on commit e2ac19b |
perfci run on commit 4d50379 |
perfci run on commit bc6a29e |
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Motivation
Enable new address modes: Add support for B address interleave and K-alignment (KRingShift) in TensileLite codegen.
Correctness in tail paths: Ensure tail global reads behave correctly when KRS is disabled at runtime (sgprKRingShift==0) by falling back to the original load-only behavior.
Performance: Reduce redundant tail offset work by hoisting invariants and interleaving offset-apply with buffer_load in the tail path.
Technical Details
BAddrInterleave (e77420a)
KRingShift align-k (cec7d49)
Tail-path refinements (5ef3eb7)
Macro/rocisa robustness (448c4d6)
Test Plan
Test Result
benchmark test for 2048x3072x1880 TN: 9% uplift
Submission Checklist