[cgmillette]

Motivation

This PR re-lands #14329. #14329 was merged into #14328's branch instead of develop and was reverted there by #14880, so develop, which now has #14328, has none of it. The commits here are #14329's, rebased onto develop, with the fixes for the review threads left open on #14329 folded into the commits they belong to (listed under "Review feedback from #14329" below), and with the new tiling CTest entry following develop's installed compiler test policy from #14868.

The tiling layer's MMA catalog (helpers/tiling/traits/data/mma_traits.json) is the table the tiling layer selects MMA instructions from and lays out their registers with. It had three problems:

• Rows clashed. Rows were keyed by op_id, so the multi-format f8f6f4 builtins loaded "last one wins".
• Operand types were name tokens (fp8bf8, iu8, ...), some of them wrong, instead of real dtypes.
• Layouts disagreed with themselves. Many rows stored two register layouts that did not match each other, or that described a K order the hardware does not use.

On top of the catalog, the tiling layer named MMA dtypes with strings, held every Fragment in its logical vector type, and found the backend instruction by searching on dtypes and shape, which could pick a different instruction from the catalog row it had selected. As a result:

• sub-byte (fp4, fp6, i4) and tf32 operands could not be moved or fed;
• mixed A/B dtypes were refused;
• integer rows with selectable signedness issued the signed instruction for unsigned data;
• a row whose result dtype differs from its accumulator could not be issued correctly.

This PR does both halves:

• Catalog. Each row describes one instruction variant with one register layout transcribed from its source, real dtypes, and real targets and intrinsics. It adds a compiler cross-check tool for the catalog, the unscaled gfx950 f8f6f4 MFMA rows, and a committed record of which rows rocke's backend issues. CTest runs the tiling package's tests.
• Dtypes. The tiling layer speaks IR dtypes end to end. Every Fragment gets a storage type under its logical dtype, and every MMA instruction is issued as the measured backend coverage record says.

The binary ABI does not change.

Technical Details

Test lane (commits 1 and 2)

1. test(rocke): make the tiling package's tests portable
   • The interleaved GEMM demo's launching tests skip unless the current GPU is a gfx90a, including on a host whose HIP runtime loads but sees no device.
   • Tests that draw a figure skip without matplotlib (an optional dependency).
   • Three tests that parse rocke's sources read them as UTF-8.
2. test(rocke): run the tiling package's tests in CTest
   • New CTest entry rocke_tiling_pytest. It runs rocke/tests/helpers/tiling from the installed package and is listed in the quick and ffm-quick categories. Every later commit runs under it.
   • Like rocke_pytest, it gets the compiler tool locations (_rocke_compiler_tool_environment) but not the compiler requirement that only the MLA entry takes (fix(rocke): scope installed compiler test policy #14868). The installed CTest environment contract test (test_installed_ctest_entries_get_scoped_environment_contracts) now checks this entry's environment too, in both layouts, with and without ROCM_PATH.
   • What it does not check: the installed tree has no rocke_engine binding, so the C++ engine cases of the IR tests skip there (their Python engine cases run; commit 23). Every test that loads platform/tools/ also skips there and the entry still passes, because the installed tree has no tools/. That is the backend coverage re-measurement, the compile of every issued MMA instruction, and the gfx950 fp8 x fp4 hardware run. They run from a source checkout only; the CMake comment and the catalog README say so.

Catalog (commits 3 to 9)

3. fix(rocke): describe one MMA instruction variant per catalog row
   • Catalog schema version 2:
     • per-operand dtypes a_dtype, b_dtype, c_dtype and d_dtype, in canonical core.dtypes names;
     • integer operand signedness, stated as selectable or signed;
     • one row per (A format, B format) for each f8f6f4 builtin;
     • integer dims and one layout_params object;
     • a scale contract on scaled rows;
     • the index layout on sparse MFMA rows (the sparse WMMA rows hold null, see commit 4);
     • auto_select: false on pin-only rows.
   • The loader is strict: any malformed row fails with a message naming the row. A dtype must be one core.dtypes.dtype_info knows, spelled by its canonical name, so an alias, a typo or a retired token (iu8) fails.
   • select() takes a=, b=, c=, an optional d=, and scale_block_k=. The selection key is (target, family, A, B, C, D, shape, scale block size).
   • TileMma refuses a row whose result dtype differs from its accumulator dtype; commit 16 lifts this.
   • Multi-block rows now load. The encoder refuses them by name.
4. fix(rocke): store one register layout per MMA catalog row, from its source
   • Each row stores one layout, the same in both of its forms (strings and layout_params).
   • The values are transcribed from the row's source: the public Matrix Instruction Calculator, the public CDNA4 ISA tables, or rocKE core's lane maps; otherwise Composable Kernel's parameters, otherwise the earlier table's strings.
   • What is checked mechanically, and nothing more: every row's strings equal the encoder's layout from its parameters; the scaled WMMA rows equal core's scaled operand layout; two calculator point facts; from commit 9, every (row, target) pair with a backend op whose lane maps core describes is compared with core's lane maps (no pair differs today); and from commit 18, one gfx950 fp8 x fp4 16x16x128 tile computes C exactly on hardware. Any other ISA-table or calculator row is as right as its transcription; the README says so.
   • The sparse WMMA rows' index operand has no source the catalog follows, so index_layout is null there; the README lists it under "Unverified layouts", and a test requires every sparse MFMA row to record one.
5. fix(rocke): list the real gfx targets and LLVM intrinsic of every MMA instruction
   • Every row lists real target ids, never family names, and every listed target is a backend target.
   • Every row names its LLVM intrinsic.
   • Targets that are excluded are recorded with a reason.
6. refactor(rocke): make the IR-validity tool's compile helpers public
   • tools/check_ir_validity.py's llvm_tool, compile_code_object, target_unsupported and first_diagnostic are public; tools/gen_arch_domain.py, rocke.tests.ir_validity and the artifact tests use the public names. Behaviour is unchanged.
7. feat(rocke): add a compiler cross-check tool for the MMA catalog
   • The scale-format codes come from core.arch.wmma_scale.SCALE_FORMATS, now public, the table the scaled WMMA lowering selects them from.
   • tools/check_mma_catalog.py asks the installed clang four questions about the catalog: on which targets each row's builtin compiles and links, which LLVM intrinsic it lowers to, which scale formats a scaled builtin accepts, and whether every matrix builtin that compiles on a backend target has a row.
   • It exits 1 on any disagreement. It names what the clang cannot judge without failing.
   • Its unit tests run no compiler and stay in the source tree. The README's edit procedure runs the tool.
8. feat(rocke): add the unscaled gfx950 f8f6f4 MFMA variants to the MMA catalog
   • One dense row per (A format, B format) pair at 16x16x128 and 32x32x64. They name the scaled builtin, which the compiler issues unscaled when both scales are zero.
   • Their layouts equal their scaled twins'.
9. feat(rocke): record which MMA catalog instructions rocke's backend issues
   • traits/data/backend_coverage.json records one measured class and the matched backend op for every (row, target) pair. It is read through load_backend_coverage(). A CoverageEntry validates its own fields when built.
   • Only issuable means the backend issues the row's instruction there. The other classes say why not, for example no_backend_op, other_instruction, multi_block, operand_form_words_only or lane_map_differs.
   • helpers/mma_io.mma_operand_ir_type is the one home of the operand-form rule.
   • A test measures the record again and requires it to equal the committed file. Because the record also lists the backend ops no row matched, adding, removing or rewiring any MMA op in core.arch fails that test until the record is regenerated; dsl_docs/development/extending.md (section 5.5), KERNEL_AUTHORING.md and the catalog README give the command and its clang requirement.

Core primitives the tiling layer builds on (commits 10 to 12)

10. feat(rocke): build zero vectors of u8 in both engines
    • IRBuilder.zero_vec takes u8 in the Python and the C++ builder alike; it lowers to <n x i8> zeroinitializer. Kernels that build no u8 zero vector lower to the same bytes as before.
11. feat(rocke): name the register-packing and storage rules in core.storage
    • REGISTER_BITS and is_register_packed(dtype); register_packing is built on them, with unchanged results and messages.
    • storage_dtype(dtype) is the one rule for what holds a dtype in registers and LDS: i32 words for sub-byte dtypes, i32 for tf32, i8 for the scale encodings e8m0 and e5m3 (SCALE_ENCODINGS, which core.ir's buffer check reads too), the dtype itself otherwise. storage_group (8 elements in 1 word at 4 bits, 16 in 3 at 6, 1 in 1 otherwise), elements_to_storage / storage_to_elements and element_bytes are the unit conversions every caller uses.
12. feat(rocke): read a compile-time integer through core.passes.constant_int
    • The constant folder's integer reader is public, so code built on the IR builder asks one function whether a value is known at compile time. The folder uses it unchanged.

IR dtypes through the tiling layer (commits 13 to 19)

13. feat(rocke): hold Fragment registers in the storage type of their dtype
    • Storage per dtype (core.storage.storage_dtype; mma_io.storage_element_type / storage_vector_type in IR types): the logical vector for arithmetic dtypes, i32 for tf32, and whole i32 words for packed sub-byte dtypes, packed low bit first.
    • An LDS buffer holds the same storage element; emit.lds_allocation(tensor, lds_swizzle) gives the buffer to allocate, and the verbs refuse any other buffer naming it. A tf32 tensor's LDS buffer is now i32 (the LLVM IR is the same).
    • Whether a tile axis can overhang its bound is one rule shared by the clip mask, the unmasked wide access and the packed-bound check.
    • fragments.storage_slots is the one rule for which storage registers hold which logical registers; register_moves.move_registers is the one register shuffle.
    • Load, store and fill move storage units in global memory and LDS; a packed access moves whole 32-bit words. A runtime origin or bound on a packed tensor's stride-1 axis is refused unless the caller passes packed_runs_aligned=True, and a packed LDS access is no wider than its start's word alignment.
    • Refusals name the fix.
    • IR for byte-or-wider dtypes is unchanged by this commit.
14. feat(rocke): take IR dtypes for A, B, C and the result in TileMma
    • a/b/c and a new d= are scalar IR types, e.g. rocke.core.ir.F16; a string is refused with TypeError naming the constant to pass.
    • A selection miss lists what the target offers.
    • MmaTraits.accepts takes IR types; MmaTraits.catalog_dtype is the one conversion from an IR type to the catalog's dtype name.
    • Every in-tree TileMma call passes IR types.
15. feat(rocke): pin MMA instructions by full signature and accept mixed A/B dtypes
    • atom_override= is the one way to pin a row. Its dtypes are optional checks; any left out are taken from the row.
    • Mixed A/B instructions (e.g. gfx942 fp8 x bf8) select and draw at each operand's own width. The recorder requires an MMA op's A and B IR types, which the views read.
16. feat(rocke): issue MMA instructions as rocke's measured backend coverage says
    • emit_op() returns the backend op the coverage record names for the (row, target) pair, using the author's A/B dtypes for selectable-signedness rows and scale_format= for multi-format scaled rows.
    • A pair that is not issuable raises with its class and what to pin instead; a record naming an op core no longer registers is refused with the regeneration to run.
    • The driver types its result by the row's result dtype. This lifts commit 3's refusal of rows whose result dtype differs from the accumulator.
    • committed_backend_coverage is exported from the traits package.
17. feat(rocke): feed MMA operands from their fragments' storage registers
    • Operands are sliced from storage registers and bitcast only to the instruction's operand form: packed words for sub-byte dtypes, i32 reinterpreted as tf32.
    • F32 fragments feed xf32 MFMAs, which truncate the low mantissa bits; the docs say when to convert to TF32 first.
    • Each subtile's result is written back with register_moves.move_registers_into.
18. fix(rocke): pair A and B K through the instruction's canonical coupling
    • Mixed-width f8f6f4 instructions hold K differently in A and B. The K check now pairs positions through the instruction's canonical layouts, so the canonical fp8 x fp4 pair is accepted and a mis-loaded operand is refused.
    • Same-format instructions are unchanged.
    • The three 32x16x128_f4 rows, whose lane holds two M blocks of A, are pin-only until their driven-tile test has run on their WMMA target's hardware.
19. feat(rocke): move fp8, bf8 and i8 fragments with vector loads and LDS stores
    • A contiguous register run of these 8-bit types moves as one <N x i8> access instead of one byte at a time, in global memory and LDS. An LDS read of an 8-bit run is an i8 read (bitcast for fp8 and bf8), so it claims the alignment of the byte run.
    • Under the built-in LDS swizzle, which moves blocks of 8 elements, an access is at most one block wide.

IR. The only C++ engine change is commit 10 (u8 in zero_vec), made in both engines. The IR of shipped kernels does not change, so byte identity and the goldens are unaffected. The IR of 8-bit fragment moves the tiling package emits changes on purpose (commit 19); no golden builds a tiling kernel, so the tiling tests pin those accesses, align included.

Engines. The tiling package is a Python-only authoring layer (now recorded in dsl_docs/development/known_gaps.md, section 9). Its IR tests run once per engine (lower_with_engine over ENGINES), and the C++ engine must emit the Python engine's IR: each form it emits (8-bit vectors, packed words, tf32 held as i32) and one single-instruction tile for every dense instruction the coverage record classes issuable. Where the rocke_engine binding is not built, as in the installed lane, only the C++ cases skip.

Review feedback on this PR (commits 20 to 23)

20. test(rocke): check that the C++ builder makes u8 zero vectors: the C++ half of commit 10 now has a test; it builds a u8 zero vector and checks that its type is a vector of u8.
21. test(rocke): lower or refuse a kernel with one named engine in tests: rocke/tests/engines.py as develop has it: lower_with_engine, assert_engine_rejects, their HIP forms and ENGINES.
22. test(rocke): gate the tiling package's gfx90a tests on the shared device check: a gfx90a_gpu fixture built on rocke.tests.gpu.current_device_arch_in replaces two local probes, so ROCKE_REQUIRE_GFX90A=1 fails instead of skipping without a gfx90a.
23. test(rocke): check the tiling MMA tests' IR with each engine: the IR tests run per engine, so their Python cases run without the binding. The engine-independent compile and link runs once, in its own test, through rocke.tests.ir_validity.assert_kernel_target_accepts.

Review feedback from #14329

The open review threads on #14329 are addressed in the commits above:

• The built-in LDS swizzle and 16-wide 8-bit runs: an access under the swizzle is at most one 8-element block (commit 19), with an IR test and a gfx90a i8 round trip.
• fp8 LDS reads claiming twice their alignment: an 8-bit LDS run is read as <N x i8> (commit 19); the tests assert align 8.
• Packed runtime bounds and origins, and the packed LDS origin: refused unless packed_runs_aligned=True; the LDS access width follows the origin's word alignment (commit 13).
• The C++ engine claim: the tiling tests lower with each engine and require the C++ engine's IR to match (lower_with_engine, commit 23); known_gaps.md records the tiling package (commit 19).
• The IR-unchanged claim and align assertions: reworded above; the regexes include align N.
• Layout wording ("hardware-exact"): reworded to what is checked mechanically (commit 4).
• The two-M-block f4 rows: pin-only (auto_select: false) until their driven-tile test has run on hardware (commit 18).
• Sparse rows without index_layout: the README lists the sparse WMMA index operand as unverified, and a test requires it on every sparse MFMA row.
• A core-only MMA change failing the coverage test: the regeneration step and its clang requirement are documented.
• The TileMma signature and stale docs, the contributor way-in ("Start here", "Adding a dtype") and three misleading messages, the API-standard items (CoverageEntry.__post_init__, TypeError, refusal tests, annotations) and the import/private-helper items (relative imports, public homes for shared rules, one clang arbiter path).
• The test-lane commit split, and the lane first, so every later commit runs under it (commits 1 and 2).
• Installed-lane coverage of the tool-backed checks: documented as source-checkout only here; staging tools/ in the installed tree, and more layout point facts with more gfx950 hardware tiles, are follow-up work (AICK-2975, AICK-2976).

Test Plan

• Catalog load: a strict-schema test for every refusal, including an unknown dtype name, a retired token and replication counts (dims R, AR, BR) that disagree; selection tests on every target, including the scaled block-size key and the multi-block refusal.
• Layouts: the two forms of every row agree; the mechanical source checks listed under commit 4; the interleave sweep over every dense row.
• Targets: every listed target is a backend target, excluded targets never appear, and every intrinsic is an llvm.amdgcn.* name.
• Cross-check tool: unit tests that classify hand-written compiler answers against real catalog rows, and the parsers' refusals.
• Backend coverage: the record is measured again and compared with the committed file; every CoverageEntry refusal, the reader's errors and the stale-record refusal are pinned.
• CTest: the installed environment contract test covers rocke_tiling_pytest in both layouts, with and without ROCM_PATH.
• Core primitives: a u8 zero vector in both engines, the register-packing predicate, the storage dtype of every kind of dtype, the storage groups and unit conversions with their refusals, element_bytes, constant_int on every kind of value.
• Storage: the storage table, storage_slots, lds_allocation for every kind of dtype, and every refusal; the align each packed and 8-bit access claims; bit-exact GPU round trips on gfx90a for tf32 through LDS, for fp4, fp6 and i4 in gfx950's canonical f8f6f4 layout through global memory and LDS (including a clipped packed window with a compile-time and a runtime bound), for u8 through LDS, and for i8 through the built-in LDS swizzle.
• Dtypes: IR-dtype refusals (TypeError) with the constant name of every scalar type, derived and default dtypes, selection by IR type on gfx90a, gfx942 and gfx950, mixed and integer selection.
• Issue: emit_op of every issuable coverage-record entry, per operand-dtype variant, returns the recorded op; every refusal text.
• Drive: a single-instruction TileMma for every issuable dense (row, target) pair lowers to the row's intrinsic with each engine, and is compiled once where the host clang targets the arch.
• K coupling: canonical mixed pairs accepted, mis-loaded operands refused. A numeric check of a driven gfx950 fp8 x fp4 tile runs where the current GPU is a gfx950; the two-M-block f4 tile's numeric check is skipped until it has run on its WMMA target's hardware.

Test Result

• Byte identity green at llvm20, llvm22, llvm23 and llvm24.
• ctest passes.
• The touched test files and the whole tiling test tree pass with both engines in strict mode, and, without the binding or the platform tools as the installed lane runs them, the IR tests' Python cases pass.
• The installed CTest environment contract test passes in both layouts (and fails with the entry's old environment).
• pre-commit passes.
• Full platform suite: no new failures. Its one failure, test_binding_compiler_selection.py::test_python_bindings_use_the_compiling_library, failed the same way on develop and passes after the rebase onto develop's fix (test(rocke): expect segment and reduce from the gfx942 tiled 3D binding #14836).
• ruff reports nothing new against develop on the changed emitter files.
• On gfx90a hardware: the tf32, fp4, fp6, i4, u8 and clipped packed-window round trips and the swizzled i8 round trip pass bit-exactly.
• gfx950: the driven fp8 x fp4 tile and the K-coupling tests pass on an MI350X at bb253bb (24 passed; the skips are the C++ engine comparisons without the binding, the gfx90a-only round trips, and a target not yet run on hardware).

ISSUE ID : AICK-2572
ISSUE ID : AICK-2576

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests.

🤖 Generated with Claude Code

[cgmillette]

Re-land of #14329 (merged into #14328's branch and reverted there by #14880). The answers to aosewski's 16 review threads are on #14329, one per thread, with commit numbers matching this PR's 19 commits. Draft until the gfx950 hardware run of the driven fp8 x fp4 tile is posted here.

[therock-pr-bot]

✅ All Checks Passed — Ready for Review

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🔎 pre-commit	✅ Pass	—
🚫 Draft PR	🔜 To Be Enabled	—
🚩 Feature Flag	🔜 To Be Enabled	—
📊 Code Coverage	🔜 To Be Enabled	—
🤖 therock-pr-bot	✅ Pass	—

🎉 All checks passed! This PR is ready for review.

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[therock-pr-bot]

🎉 All checks passed! This PR is ready for review.

[cgmillette]

Code-quality pass on this PR's own code, folded into the commits that introduced it (no rebase onto develop):

• One storage rule. core.storage.storage_dtype now says what holds each dtype in registers and LDS (i32 words for sub-byte, i32 for tf32, i8 for e8m0/e5m3, else the dtype), with storage_group, elements_to_storage / storage_to_elements and element_bytes as the unit conversions. mma_io.storage_element_type / storage_vector_type give it in IR types; the copies in fragments.py, emit.py and mma_io (packed_register_type) are gone, and mma_io.storage_ir_type reads the same rule. The scale-encoding list has one home (core.storage.SCALE_ENCODINGS), which core.ir's buffer check now reads.
• LDS allocation. New public lds_allocation(tensor, lds_swizzle) returns (element type, count); the buffer check, tests and docs use it. A tf32 tensor's LDS buffer is now i32 like its registers; the LLVM IR of every tiling kernel I compared (demos, LDS-staged, tf32/packed/u8 round trips, fp8/i8 LDS kernels; 29 kernels) is byte-identical before and after.
• One bound rule in emit.py for "can this tile axis overhang", used by the clip mask, the unmasked wide access and the packed-bound check.
• Catalog: replication (dims R, AR, BR) is checked at load with an error naming the row; legacy_table provenance is now earlier_generated_table; MmaTraits.accepts takes IR types and MmaTraits.catalog_dtype is the one IR-type-to-name conversion (selection, pinned-instruction check, emit_op).
• Smaller items: the scale-format codes are public in core.arch.wmma_scale.SCALE_FORMATS and the catalog tool imports them; lds_conflict no longer imports a private helper; committed_backend_coverage is exported from traits; the two-M-block refusal lives in InterleavedStyle; the driver's private register copy is replaced by move_registers_into; register_moves and the recorder are typed, and a recorded MMA op must carry its A/B IR types; LDS buffer errors share one wording with the verb prefix, and the bitcast fix text has one helper.
• Not done here: checking that each row's layout strings equal its layout parameters at catalog load. That needs the MMA-layer encoder (an upward import from traits) and costs a few seconds per load for 318 rows, so it stays a test for now; open question for the owner.

Gates: byte identity green at llvm20/22/23/24; touched tests pass with both engines in strict mode; platform + tiling suites show no new failures; pre-commit passes.

[cgmillette]

GPU check at head bb253bb on gfx950 (MI350X): test_mma_k_coupling.py (incl. the driven fp8 x fp4 tile) and the fragment storage round-trip selection -- 24 passed, 11 skipped (C++ engine comparisons without the binding, gfx90a-only round trips, and a target not yet run on hardware). Ready for review.

[BrianHarrisonAMD]

Approving for dnn-providers (changes are not related)

[cgmillette]

Rebased onto current develop to clear the merge conflict.

• One conflict, in platform/tests/test_engine_linkage.py: develop now passes -DCMAKE_PROJECT_INCLUDE=... (executable-suffix coverage) and this PR passes -DROCKE_PYTHON_INSTALL_DIR=python (the tiling CTest entry's fixed install path). The resolution keeps both arguments; the installed-CTest environment test passes in all four parametrizations.
• No other commit changed (range-diff: 18 of 19 commits identical). No develop code uses the helpers this PR moved: the scale encodings, storage rules, constant_int, the MMA catalog dtype and the IR-validity tool helpers each still have one home.
• Checks: C++ and Python engines byte-identical at llvm20, llvm22, llvm23 and llvm24; ctest green; tiling tests green with both engines in strict mode; platform tests show no new failures against develop; pre-commit clean.

[CongMa13]

No new issues found.

[cgmillette]

Automated review: Model - qwen3.6:35b-a3b-coding-mtp-q4_K_M, effort: max

PR #15007 — feat(rocke): one exact MMA catalog row per instruction variant, and IR dtypes through the tiling layer (cgmillette, AICK-2572, AICK-2576) — 🟠 First-round: IR tests skip in CI

Prior item	Status
BrianHarrisonAMD, AnaghaRaoAMD (11-04) approvals	🟢 APPROVED bb253bb7e6 • older head; still counts on develop • not covered: the rebase's merge with 12167's test_engine_linkage.py change (ran)
CongMa13 (11-04) approval	🟢 APPROVED ab34eaca55 • current head
aosewski (11-02) 16 threads on 14329	🟠 DEFERRED (record re-measurement) • all 16 answered on 14329; no reply yet (read) • AICK-2975, "larger change": moving only the re-only parser un-skips CI's record check • engine-parity answer skips whole in CI: N1
Our 10-29 N2 (14537, then 14329): 8-bit LDS reads claim align 16	🟢 FIXED ab34eaca55 • reads are <8 x i8> align 8, as lane offsets allow (ran)
Copilot (10-28, 14537): mixed-width K pairing, no numeric check	🟡 DEFERRED (gfx1250) • fp8 x fp4 tile passed on gfx950 hardware: author's run (read) • gfx1250 f4 rows pin-only until hardware: fair (read)
14329's revert, 14880 (11-02)	🟢 Cause gone • no reason given; it undid a merge into 14328's branch (read) • head targets develop; lane uses 14868's tool environment (read)
Develop issue 14667 (Windows cp1252 scans)	🟡 Code fixed, CI owed • 3 scans pass under a CP1252 locale, mutation included (ran) • Windows-shard criterion waits for this PR's first test run
Bots / CI	🟡 Red, develop's • fails: 4 math-libs builds — develop's 14976 broke the hipCCL configure (read) • no test job ran: run's develop predates revert 15089; needs a push • predicted: Windows test step nears its 30-min limit; confirm on the shard • merge: clean; 24 ✓
Our checks	🟢 Clean • merge vs 8b6ada3287: clean, 44 behind (ran) • build + ctest 46 ✓ / 1 skip; byte identity ×4, all families; goldens unchanged (ran) • whole tiling tree, both engines strict: 3011 ✓, 39 GPU skips (ran) • coverage record same at llvm24; compile, rules clean (ran)
Code quality	🟠 Should-fix • IR claim tests skip in CI: N1; record re-measurement: aosewski row (ran) • C++ u8 zero_vec admission has no test: N2 (ran) • i8 LDS reads detour around core's fp8 align over-claim: fix core separately (ran)

#	Sev	file:line	Finding
N1	🟠	platform/python/rocke/tests/helpers/tiling/mma/test_mma_issuable_pairs.py:121	IR-claim tests skip whole without rocke_engine, as in CI • impact: 374 cases in six files never reach their IR checks in CI's lane (ran) • fix: develop's lower_with_engine over ENGINES (14842) keeps the Python half in CI; update CMakeLists.txt:673
N2	🟠	platform/cpp/core/ir/ir_arith.cpp:131	C++ half of "zero_vec takes u8" has no test • impact: reverting the C++ line passes every test (ran) • fix: CHECK(rocke_b_zero_vec(&b, rocke_u8(), 8) != NULL); at test_f64_lowering.cpp:276
N3	🟡	platform/python/rocke/tests/helpers/tiling/test_fragment_storage.py:671	GPU gates and test helpers copied, not reused • impact: copies skip where ROCKE_REQUIRE_GFX90A=1 must fail (read) • fix: one fixture on rocke/tests/gpu.py's current_device_arch_in; public _compile_or_skip

Utility: 🟢 Positive — exact MMA rows, IR dtypes and a tiling CI lane; fixes 14667

---

Legend: 🔴 blocking · 🟠 should-fix · 🟡 minor nit · 🟢 info/good · ⚪ retracted

First-round review: first pass by a local qwen3.6 model, verified by the orchestrator (Claude Opus 5.5). Checks: merge with develop, build + ctest, byte identity and goldens at four flavors, the whole tiling tree (both engines, and installed as CI runs it), a CP1252 locale run, the coverage record at llvm24, CI logs against develop's own runs, code quality. Flags whether a closer look is needed; not an approval or rejection.

[cgmillette]

GPU results at ab34eac (Python engine; the tiling test tree):

• gfx950 (MI350X): 2537 passed, 513 skipped, 0 failed. The skips are cases for other GPUs (for example "needs a gfx90a GPU") and targets the host compiler cannot build for.
• gfx90a (MI210): 2580 passed, 472 skipped, 0 failed. 470 of the skips are the both-engine comparisons, which need the C++ engine binding that this run did not build; those comparisons run in the CPU lanes.

The red Stage - Math Libs checks on this head are develop's hipCCL configure break (#14976, reverted by #15089), not this PR; the next push or develop merge picks up the revert.

[cgmillette]

Addressed the latest automated review in four commits on top of ab34eaca556. No rebase, and no emission change, so goldens and byte identity are unaffected.

• N1 (IR tests skip in CI). The IR tests in the six tiling files are now parametrized over ENGINES and lower through lower_with_engine. The Python case runs in every lane, including CI's installed tiling lane, which has no rocke_engine binding. The C++ case also checks that the C++ engine emits the same IR. Only the C++ case skips without the binding.
  • The helper is develop's rocke/tests/engines.py, brought in unchanged, so it merges as a no-op.
  • Compiling a module does not depend on the engine, so each compile now runs once, in its own test, through a public rocke.tests.ir_validity.assert_kernel_target_accepts.
  • The comment on the installed tiling CTest entry now lists the new skip.
  • Check: in a run with neither the binding nor the platform tools (as CI runs), changing the expected intrinsic count makes all 339 issuable-pair cases fail. Before this change they skipped.
• N2 (C++ u8 zero_vec untested). test_f64_lowering.cpp now builds an 8-lane u8 zero vector and checks that its type is a vector of u8.
  • Check: dropping u8 from rocke_b_zero_vec fails rocke_f64_lowering. Expecting i8 instead also fails it.
• N3 (GPU gates copied).
  • A gfx90a_gpu fixture in the tiling conftest.py replaces the local gfx90a probes in test_fragment_storage.py and test_lds_descriptor_addressing.py. It uses rocke.tests.gpu.current_device_arch_in, so ROCKE_REQUIRE_GFX90A=1 now fails instead of skipping.
  • The private _compile_or_skip is replaced by the public helper above.
• aosewski's threads (record re-measurement). No code change here. This stays deferred to the follow-up already tracked, as answered on feat(rocke): one exact MMA catalog row per instruction variant, and IR dtypes through the tiling layer #14329.
• Copilot (mixed-width K pairing). Unchanged. The fp8 x fp4 tile is checked on gfx950 hardware; the other f4 rows stay pin-only until they have run on hardware.
• [rocke] test_accesses.py::test_the_range_marker_is_stated_only_by_its_checked_callers fails on Windows since #13876 (read_text() decodes UTF-8 sources as cp1252) #14667 (Windows cp1252 scans) and CI. These need this push's CI run. The red math-libs builds come from develop's hipCCL configure.

Gates:

• Build and ctest: 47 of 47 pass.
• Whole tiling tree, both engines strict: 3714 passed, 72 skipped.
• Whole tiling tree without the binding or platform tools, as CI runs it: 2929 passed, 857 skipped. Before: 2555 passed, 497 skipped. Run time grew by about 5% on this host.
• Platform suite: same results as the base head.
• pre-commit: clean.

[cgmillette]

Automated review: Model - qwen3.6:35b-a3b-coding-mtp-q4_K_M, effort: max

PR #15007 — feat(rocke): one exact MMA catalog row per instruction variant, and IR dtypes through the tiling layer (cgmillette, AICK-2572, AICK-2576) — 🟠 Follow-up: N1–N2 fixed; re-measurement deferred

Prior item	Status
BrianHarrisonAMD, AnaghaRaoAMD, CongMa13 (11-04) approvals	🟢 APPROVED bb253bb7e6, ab34eaca55 • older heads; still count on develop • since ab34eaca55: 4 test commits, 1 CMake comment; approved code unchanged (read) • bb253bb7e6 also predates the rebase's test_engine_linkage.py merge (read)
aosewski (11-02) 16 threads on 14329	🟠 DEFERRED (record re-measurement) • no reply since 11-03; engine-parity part now runs in CI: N1 (read) • author: "stays deferred to the follow-up already tracked" (AICK-2975) • judgement: fits staging tools/, not the small re-only parser move
Copilot (10-28, 14537): mixed-width K pairing, no numeric check	🟡 DEFERRED (gfx1250) • unchanged: fp8 x fp4 checked on gfx950 hardware, author's run (read) • two-M-block f4 rows pin-only, numeric test skipped until gfx1250: fair (read)
Develop issue 14667 (Windows cp1252 scans)	🟡 Code fixed, CI owed • both scans pass under a CP1252 locale at this head (ran) • Windows rocKE shards not run yet: sanity test queued (read) • predicted: Windows Test step nears its 30-min limit; confirm on the shard
Ours 11-05 N1: IR-claim tests skip whole without rocke_engine	🟢 FIXED 9a46be603b • as CI runs it: 339 Python pair cases run; a doubled count fails all 339 (ran) • saved probe FIXED at head; retired (ran) • left: known_gaps.md:335 still names lower_with_both_engines; say lower_with_engine over ENGINES
Ours 11-05 N2: C++ half of "zero_vec takes u8" untested	🟢 FIXED f7de7f1dfb • u8 dropped: rocke_f64_lowering aborts; i8 expected: it fails (ran) • the hipDNN Linux superbuild runs it at head: passed (read)
Ours 11-05 N3: GPU gates and test helpers copied	🟡 PARTLY FIXED 0ccb59db83 • ROCKE_REQUIRE_GFX90A=1 now fails 25 cases; compile helper public (ran) • the demo's own gate (test_tiling_gemm_interleaved_demo.py:29) still skips its 9 (ran) • fix: usefixtures("gfx90a_gpu") on its 4 tests; drop the fixture and import (ran)
Bots / CI	🟡 Running • fails: emulation stage — runner shutdown mid-step; develop's own run hit it too (read) • Linux test jobs skipped behind it; the auto-retry re-runs it once the run ends (read) • queued: Windows sanity test, artifact check; PR bot cancelled (read) • merge: clean; 27 ✓; blocked on Multi-Arch CI Summary
Our checks	🟢 Clean • merge vs 3d6c617f50: clean; same provider tree as the checks' merge (ran) • ctest 48 ✓ / 1 skip; byte identity ×4, all families; goldens unchanged (ran) • changed tests 3441 ✓; whole installed tiling lane 2894 ✓ / 890 skip, 0 ✗ (ran) • engines.py is develop's blob, byte for byte (ran)
Code quality	🟡 Minor • N2 fixed (ran); N1 fixed, engines.py is develop's (read) • demo's own gfx90a gate still skips under REQUIRE: N3 row (ran) • shared _calls also counts a .tied twin; _intrinsic_calls does not (ran)

Utility: 🟢 Positive — N1 and N2 fixed; the tiling IR checks now run in CI

---

Legend: 🔴 blocking · 🟠 should-fix · 🟡 minor nit · 🟢 info/good · ⚪ retracted

Follow-up review: first pass by a local qwen3.6 model, verified by the orchestrator (Claude Opus 5.5). Checks: merge with today's develop, build + ctest, byte identity and goldens (4 flavors), changed tests and the whole tiling lane (installed, as CI runs it), mutation checks of N1–N3, CP1252 scans, CI logs against develop's runs, code quality. Flags whether a closer look is needed; not an approval or rejection.

[cgmillette]

Automated review: Model - qwen3.6:35b-a3b-coding-mtp-q4_K_M, effort: max

PR #15007 — feat(rocke): one exact MMA catalog row per instruction variant, and IR dtypes through the tiling layer (cgmillette, AICK-2572, AICK-2576) — 🟠 Follow-up: clean merge; re-measurement deferred

Prior item	Status
BrianHarrisonAMD, AnaghaRaoAMD, CongMa13 (11-04) approvals	🟢 APPROVED bb253bb7e6, ab34eaca55 • older heads; still count on develop • not covered: 11-05's 4 test commits; bb253bb7e6 also the rebase's linkage-test merge (read) • develop merge automatic; the PR's own diff unchanged (ran)
aosewski (11-02) 16 threads on 14329	🟠 DEFERRED (record re-measurement) • unchanged: no reply on 14329 since 11-03 (read) • CI still skips its 3 cases (read); they pass on the merge here (ran) • AICK-2975; judgement stands: fits staging tools/, not the small re-only parser move
Copilot (10-28, 14537): mixed-width K pairing, no numeric check	🟡 DEFERRED (gfx1250) • unchanged: two-M-block f4 numeric test still skipped (read) • fp8 x fp4 checked on gfx950 hardware, author's run: fair (read)
Develop issue 14667 (Windows cp1252 scans)	🟡 Code fixed, CI owed • both scans pass under CP1252 on the merge; control read fails (ran) • no Windows rocKE shard has run at any head yet (read) • predicted: the new lane may push Azure-pool shards past the 30-min limit
Ours 11-05 N1, N2: IR tests skip in CI; u8 zero_vec C++ test	🟢 FIXED 9a46be603b, f7de7f1dfb • N1 holds in CI: Python IR cases pass on both Linux shards (read) • left: known_gaps.md:335 still names lower_with_both_engines (read)
Ours 11-05 N3: GPU gates and test helpers copied	🟡 PARTLY FIXED 0ccb59db83 • demo gate (test_tiling_gemm_interleaved_demo.py:29) still skips under REQUIRE: use gfx90a_gpu (ran) • _run (test_fragment_storage.py:673) repeats develop's launch_with_buffers, merged in here: call it (ran) • _IntBuilder (test_mma_backend_coverage.py:238) now repeats rocke.tests.lane_maps: read lane_placements (ran)
Bots / CI	🟡 Running • Linux gfx94X shards 2/2 ✓, tiling lane included (read) • queued: Windows sanity since 00:20Z, no runner; Windows shards after it (read) • merge: clean; 38 ✓; Multi-Arch CI Summary owed; auto-merge armed
Our checks	🟢 Clean • merge vs 41d662e653, 14832 included: clean, 4 behind; goldens unchanged (ran) • at 30056c12cf: ctest 48 ✓ / 1 skip; byte identity ×4, all families (ran) • changed tests 3441 ✓, installed 2528 ✓; coverage record re-measured: equal (ran)
Code quality	🟡 Minor • merge automatic; engines.py is develop's file, one version (ran) • N3: demo gate, launcher, lane-map evaluator still copied (ran) • _calls and known_gaps.md items unchanged (ran)

Utility: 🟢 Positive — clean develop merge; the tiling lane passes on both Linux shards

---

Legend: 🔴 blocking · 🟠 should-fix · 🟡 minor nit · 🟢 info/good · ⚪ retracted

Follow-up review: first pass by a local qwen3.6 model, verified by the orchestrator (Claude Opus 5.5). Checks: merge with today's develop and the head's remerge-diff, build + ctest, byte identity and goldens (4 flavors), changed tests (source and installed), the coverage re-measurement on the merge, CP1252 scans, CI logs and recent Windows shard times, code quality. Flags whether a closer look is needed; not an approval or rejection.

[Copilot]

🟡 Changes recommended

The MMA compatibility check can accept layouts that pair different logical K values, allowing incorrect GEMM results.

4 open issues

• Validate K coupling across all output rows and columns · New
• Preserve operand orientation when checking K coupling · New
• Use the enforcing gfx90a fixture for GEMM tests · New
• Document the per-engine lowering test pattern · New

What changed in this PR

Re-lands rocKE’s instruction-variant MMA catalog work and carries IR dtypes through the tiling authoring layer, supporting mixed-format operands and packed register storage without changing the binary ABI.

Changes:

• Introduces storage-aware fragment shuffles and typed A/B/C/D MMA APIs, recorder metadata, and visualization.
• Checks operand K alignment through canonical instruction coupling and explicitly rejects unsupported layouts.
• Adds portable tests, per-engine instruction checks, and a scoped installed tiling CTest entry; documents source-only validation gaps.

File	Description
dnn-providers/​hip-kernel-provider/​rocke/​TESTING.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​style/​API_DESIGN_STANDARD.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tools/​gen_arch_domain.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tools/​check_ir_validity.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​tools/​test_arch_domain_artifact.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​test_engine_linkage.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​core/​test_zero_vec_and_lds_element_types.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​core/​test_storage.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​core/​test_mma_io.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​core/​test_f64_lowering.cpp	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​tests/​core/​test_constant_int.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​ir_validity.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​visualization/​test_layout_render.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​visualization/​test_block_diagram.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​visualization/​test_auto_pipeline.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​traits/​layout_descriptor.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_transforms.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_scheduling.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_lds_conflict.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_layout_optimizer.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_fragment.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_emit_wide_access.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​test_coalescing_probe.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​tensor_transforms/​test_accesses.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​mma/​test_warp_encoding.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​mma/​test_mma_validation_recipe.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​mma/​test_mma_issuable_pairs.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​mma/​test_layout_styles.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​mma/​test_layout_oracle.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​kernels/​test_tiling_gemm_interleaved_demo.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​tests/​helpers/​tiling/​conftest.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​visualization/​layout_render.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​visualization/​auto_pipeline.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​transforms/​verb.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​transforms/​observers.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​transforms/​_core.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​traits/​__init__.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​tiling_recorder.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​register_moves.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​README.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​mma/​warp_encoding.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​mma/​styles/​interleaved.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​mma/​styles/​base.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​mma/​mma_operation.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​memory.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​lds_conflict.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​layout_optimizer.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​kernels/​tiling_gemm_interleaved_demo.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​kernels/​tiling_gemm_crc_demo/​crc_interleaved_gemm.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​docs/​visualization_api_surface.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​docs/​mma_is_machinery.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​docs/​lds_banks.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​docs/​api_proposals/​PROPOSAL_c_transpose_crossed_ab.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​descriptors.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​analysis/​soundness.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​analysis/​geometry.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​.claude/​team_members/​lds_expert.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​.claude/​skills/​rocke-tiling-api/​SKILL.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​.claude/​skills/​layout-viz/​SKILL.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​tiling/​__init__.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​helpers/​mma_io.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​core/​storage.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​core/​passes.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​core/​ir.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​python/​rocke/​core/​arch/​wmma_scale.py	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​reference/​dtype_support.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​optimization/​arch/​gfx942.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​ir_lowering/​ir_model.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​development/​known_gaps.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​development/​extending.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​architecture/​multi_arch_data_layout.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​dsl_docs/​architecture/​gfx_support_audit.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​cpp/​core/​ir/​ir_arith.cpp	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​cpp/​core/​ir/​core_types.cpp	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​CMakeLists.txt	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​platform/​AGENTS.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​rocke/​KERNEL_AUTHORING.md	Updated as part of this pull request.
dnn-providers/​hip-kernel-provider/​ROCKE_ENGINE_test_categories_external.yaml	Updated as part of this pull request.

_{Review effort: Max}