[cgmillette]

Motivation

buffer_load_vN and buffer_store_vN move u8 and i64 elements, and the LLVM route lowers them (<N x i8>, <N x i64>). The HIP route had no vector type for either, so a kernel that uses one failed to build with no HIP mapping for type vec<u8xN> / vec<i64xN>. This brings the HIP route to parity, in both engines.

Technical Details

Two commits, each in both engines with identical HIP source.

1. One vector-name table per HIP lowering (refactor). Python _type_to_hip now reads _VEC_PREFIX instead of repeating it in an if-chain. In C++ the three copies of the list (rocke_h_vec_prefix, its membership check and the check in rocke_h_type_to_hip) become one table; rocke_h_vec_prefix returns NULL for an element with no vector type, and its unused full_map flag and "f16x" fallback are gone. No output change.
2. u8 and i64 vectors on the HIP route (feat). The table gains u8 -> u8xN (uint8_t) and i64 -> i64xN (int64_t).
   • The shared prologue is unchanged. A kernel that uses one of these vectors gets using u8xN = uint8_t __attribute__((ext_vector_type(N))); (or the i64 form) right after the prologue, through the existing per-kernel declaration path that already covers widths the prologue does not declare. So the HIP source of every existing kernel stays the same and no golden is re-recorded.
   • A u8 vector now reaches the vector ops, so vector.smax, vector.smin and vector.sext refuse an unsigned operand on the HIP route as they already do on the LLVM route, with the same message.
   • With the per-lane-width lshr lowering that fix(rocke): shift HIP vector lshr lanes in their own width #14844 added to develop, vector.lshr on u8 lanes reads them as uint8_t and on i64 lanes as uint64_t.
   • op_vocabulary.md no longer says u8 / i64 buffer accesses lower through LLVM only.

Test Plan

• tests/core/test_buffer_access_widths.py: u8 (1, 4, 16) and i64 (1, 2) added to every width check (LLVM IR, both-engine LLVM IR and HIP source, builtin per width); a new test checks the per-kernel declaration follows the prologue once and the prologue has no u8 / i64 vector; the hipcc compile of every width now runs for gfx942 and gfx950; the GPU bit-exact copy through both compile routes covers u8 and i64.
• tests/core/test_vector_lshr.py (added by the lshr fix): u8 and i64 lanes added to the both-engine HIP source check, the hipcc compile for gfx942 and gfx950, and the GPU comparison of the LLVM route and hipcc on the both-engine HIP source against numpy on lanes with the top bit set and clear.
• tests/core/test_u8_arith.py: the HIP lowerings refuse a signed vector op on u8 with the LLVM message (they used to stop earlier on the missing type). tests/core/test_amdgpu_lowering_ops.py: the unsupported-element refusal now uses fp4e2m1, since i64 is supported.
• HIP output unchanged: every config of every parity emitter lowered to HIP with the lshr fix branch and with this branch, Python and C++ engines.
• Byte identity at llvm20, llvm22, llvm23, llvm24; ctest; touched tests; pre-commit.

Test Result

• Byte identity GREEN at llvm20, llvm22, llvm23 and llvm24.
• HIP output: 803 parity-emitter kernels; Python engine 765 lowered, 38 refused; C++ engine 524 lowered, 279 refused (no C++ HIP lowering for those ops on develop either). Text and refusals identical between the lshr fix branch and this branch, in each engine.
• ctest: 34 passed, 1 skipped (rocke_arch_domain_reproducibility, which needs its measuring compiler). Touched tests (test_vector_lshr.py, test_buffer_access_widths.py, test_u8_arith.py, test_amdgpu_lowering_ops.py, test_mma_io.py): 277 passed with both engines (strict), including the GPU tests on a local gfx90a and the hipcc compiles for gfx942 and gfx950.
• Before the lshr fix was split out, the same code on an older develop passed the full platform suite (platform/tests) except 2 tests that fail the same way on develop in that environment (test_arch_domain_lane.py::test_the_cpp_fallback_does_not_warn_twice, test_binding_compiler_selection.py::test_python_bindings_use_the_compiling_library). Each commit was built and tested on its own. Pre-commit clean.

ISSUE ID : AICK-2862

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[cgmillette]

Rebased onto develop now that #14844 (the per-lane-width vector.lshr fix) has merged. The branch holds only this PR's two commits, unchanged (git range-diff shows both patch-identical), at 27017997437; the merge conflict is gone.

Re-run on the new head: byte identity green at llvm20, llvm22, llvm23 and llvm24; ctest 34 passed, 1 skipped; the touched tests (test_vector_lshr.py, test_buffer_access_widths.py, test_u8_arith.py, test_amdgpu_lowering_ops.py, test_mma_io.py) pass with both engines in strict mode, including the GPU checks on gfx90a and the hipcc compiles for gfx942 and gfx950. The description no longer says this depends on #14844, and its ctest line is corrected.