fix(rocke): bound gfx942 3D KV cache by its K/V loader by dlangbe · Pull Request #14216 · ROCm/rocm-libraries

dlangbe · 2026-10-22T19:13:02Z

JIRA ID : AICK-2716

Motivation

#12446 lowered the i64 KV-addressing threshold for the tiled builders from > 0x80000000 to > 0x7FFF0000 bytes (_I32_KV_BUFFER_BYTES), the bound of the async buffer loads. The gfx942 tiled 3D kernel has no i64 path, and its spec refuses use_i64_kv_addr. So gfx942 decode on a paged KV cache of exactly 2 GiB, which ran correctly before #12446, now fails with NotImplementedError: gfx942 tiled 3D kernel does not support use_i64_kv_addr.

The failing shapes are bf16 decode with B=64, Skv=32768, Hkv=4, D=128, block size 16, and Hq=64 or 32: 131072 blocks of 16 KiB, exactly 2^31 bytes. The 0x7FFF0000 bound only applies to the async buffer copies. These shapes use the wide K/V loader (use_wide_kv_load), a flat global load indexed by an i32 byte offset, which reads correctly below 2^31 bytes. The fp8 dequant loader is the same kind of load.

Technical Details

Changes

kernels/gfx942/attention_tiled_3d.py: wide_kv_load_fits(tile_size, head_size) is the builder's WIDE_OK test, now shared. i32_kv_cache_bytes(...) returns the largest cache the selected loader reads: 2^31 bytes for the wide and fp8 loaders, 0x7FFF0000 for the async copies. Updated the use_i64_kv_addr field comment.
kernels/common/attention_unified.py: gfx942_3d_kv_needs_i64_addr(...) is the single rule. _enable_i64_kv_addr_3d(problem, arch) applies it to a problem on gfx942 and returns _enable_i64_kv_addr on every other arch. Below the buffer range it returns early, so the cache key skips the selector walk.
Call sites: _spec_generic_3d, _tiled_3d_cache_key, AttentionTuningSpec.with_num_kv_blocks (gfx942 3D), and make_explicit_attention_3d_specs (gfx942).
3D launch guard: _run_3d_tiled_on_stream checks the real paged cache against the segment kernel's limit (_3d_spec_kv_addr_limit: the loader limit on gfx942, _spec_kv_addr_limit on gfx950), memoized per cache key in _3D_KV_ADDR_LIMITS. A caller with a stale positive num_kv_blocks is refused instead of reading a wrapped address. Strided K/V and gfx1250 are not checked.

Behaviour change

gfx942 3D on the wide or fp8 loader: caches up to 2^31 bytes stay i32 (previously refused above 0x7FFF0000). Above 2^31 bytes they are still refused.
gfx942 3D on the async copies (HIPDNN_GFX942_3D_WKV=0, head size 256, or a tile the wide loader can't split): unchanged, refused above 0x7FFF0000.
gfx950, gfx1250 and all 2D paths: unchanged.
Emitted gfx942 3D IR is unchanged.

Test coverage

New TestGfx942Tiled3DKvAddr in test_selector_parity.py covers:
- the per-loader limits
- both shapes building on the wide loader without i64 at exactly 2 GiB
- refusal one block past 2 GiB on the wide loader
- refusal at exactly 2 GiB with the wide loader off
- the 3D cache key sharing across caches the loader reads and splitting past its limit
- the explicit 3D spec and with_num_kv_blocks following the loader limit
test_tuning_space.py::test_runtime_cache_size_specializes_i64_but_keeps_the_id asserted that a wide-loader gfx942 3D spec is refused at 65535 blocks of 32 KiB. It now checks each loader at its own limit.

Differential: PR base vs this branch

The 3D i64 decision through the spec builder (_tiled_3d_spec_from_problem), the 3D cache key (does it share the key of a 1-block cache) and AttentionTuningSpec.with_num_kv_blocks on an explicit 3D spec, over 288 cases: gfx942/gfx950, fp8 on/off, head size 64/128/256, block size 16/32, 4/8 KV heads, HIPDNN_GFX942_3D_WKV default/0 (gfx942). Base is a04f810197d5. Changed cells in bold.

arch	K/V loader	cache size	spec: base → branch	key shares small-cache key	tuned bind	cases
gfx942	wide	≤ 0x7FFF0000	i32 → i32	yes → yes	i32 → i32	8
gfx942	wide	0x7FFF0000 + 1 block	refused → i32	no → yes	refused → i32	8
gfx942	wide	2^31	refused → i32	no → yes	refused → i32	8
gfx942	wide	2^31 + 1 block	refused → refused	no → no	refused → refused	8
gfx942	async	≤ 0x7FFF0000	i32 → i32	yes → yes	i32 → i32	16
gfx942	async	0x7FFF0000 + 1 block and above	refused → refused	no → no	refused → refused	48
gfx942	fp8 dequant	≤ 0x7FFF0000	i32 → i32	yes → yes	i32 → i32	24
gfx942	fp8 dequant	0x7FFF0000 + 1 block	refused → i32	no → yes	refused → i32	24
gfx942	fp8 dequant	2^31	refused → i32	no → yes	refused → i32	24
gfx942	fp8 dequant	2^31 + 1 block	refused → refused	no → no	refused → refused	24
gfx950	async / fp8 dequant	≤ 0x7FFF0000	i32 → i32	yes → yes	i32 → i32	24
gfx950	async / fp8 dequant	0x7FFF0000 + 1 block and above	i64 → i64	no → no	i64 → i64	72

64 of 288 cases differ, all gfx942 wide or fp8 caches between 0x7FFF0000 and 2^31 bytes.

Test Plan

Full library/tests on CPU (one pytest per file, GPU hidden): 15213 passed, 3547 skipped, 30 failed in 17 files; the same 30 tests fail on the PR base a04f810197d5, none only on this branch. 5 attention-backward files exceeded a 20-minute per-file limit; this PR does not touch backward attention.
Mutation check: with the old rule patched back in, three of the new tests fail (the exactly-2-GiB build for both head counts, the 3D cache key, and the explicit spec / with_num_kv_blocks). The two refusal tests pass either way, since they guard the other direction.
IR identity: Python-lowered gfx942 3D IR (llvm22) for 96 specs (head size 64/128/256, block size 16/32, full and half tile, wide on/off, fp8 on/off, GQA 1 and 8) is byte-identical to develop. The C++ engine is untouched; the byte-identity gate was not rerun.
gfx942 GPU, through run_unified_attention_torch against an fp32 torch reference, on a cache of exactly 2^31 bytes whose block table is a random permutation of the whole cache. 4 sequences read blocks at or past 0x7FFF0000. Both shapes ran on the wide loader without i64:
- Hq=64: max_abs 1.4e-4 on the sequences that read those top blocks, 1.4e-4 on the rest.
- Hq=32: max_abs 1.1e-4 on the top-block sequences, 1.3e-4 on the rest.
gfx942 GPU, a cache one block past 2^31 bytes: both shapes are refused when the spec is built.
Review fixes: TestGfx942Tiled3DKvAddr adds test_3d_launch_checks_the_real_cache (gfx942, wide and async loaders) and test_gfx950_3d_launch_checks_the_real_cache (stale count refused past the buffer range; real count builds i64 and passes). With the guard disabled both fail.
gfx942 GPU, both shapes on the 3D path (device CU count) with a stale num_kv_blocks=1024: an exactly 2^31-byte cache runs and matches the reference; one block past is refused by the launch guard at 2^31 bytes.
gfx942 GPU: test_attention_tiled_3d_kv_lds_swizzle.py and test_attention_tiled_3d_wave_page_id_load.py (-k gfx942): 48 passed, 12 skipped. test_strided_kv_decode_numeric.py with ROCKE_REQUIRE_DECODE_GPU=gfx942: 74 passed.

Submission Checklist

Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests.

The gfx942 tiled 3D kernel has no i64 path, and #12446 made it refuse any paged cache above 0x7FFF0000 bytes, the async buffer bound. Its wide and fp8 loaders are flat i32-byte-offset loads that read up to 2^31 bytes, so 2 GiB decode caches that ran correctly before are now refused. Decide the gfx942 3D i64 flag from the selected loader's limit, through one rule shared by the spec builder, the 3D cache key and the dispatcher's tuning specs. Emitted IR is unchanged.

therock-pr-bot · 2026-10-22T19:18:25Z

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therock-pr-bot · 2026-10-22T19:18:29Z

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🟢 Approval recommended

Loader-specific limits are applied consistently across the affected paths, with boundary regression coverage and reported GPU and IR-identity validation.

No open issues 🎉

What changed in this PR

Fixes the gfx942 tiled 3D attention regression introduced by #12446 by matching the KV-cache size limit to the selected loader. This restores support for exactly 2 GiB caches on wide and fp8 loaders while retaining the stricter async-copy limit.

Changes:

Shares loader eligibility and cache-limit logic without changing emitted kernel IR.
Applies the loader-specific limit consistently to spec construction, cache keys, and tuning-spec specialization.
Adds boundary tests for supported caches, oversized-cache rejection, and cache-key behavior.

File	Description
`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py`	Adds loader-limit, spec-construction, and cache-key regression tests.
`dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py`	Checks runtime specialization at each loader’s boundary.
`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py`	Extracts wide-loader eligibility and defines loader-specific cache limits.
`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py`	Centralizes the gfx942 3D addressing decision and updates cache keys.
`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py`	Applies the loader limit when constructing explicit 3D specs.
`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py`	Uses the bound spec’s loader when specializing runtime cache size.
`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py`	Uses the 3D-specific addressing decision during spec construction.

_{Review effort: Balanced}

yraparti

rocKE checklist review

ROCm/rocm-libraries#14216 · c9c73c2a8e85 · model gemini-4-argon, fallback gpt-5.5

PASS · graded 238/238 · BLOCKER 0, HIGH 3, MEDIUM 1, LOW 0, NEEDS-INFO 2

Findings

HIGH §A · dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 · Mirror gfx942_3d_kv_needs_i64_addr and _enable_i64_kv_addr_3d in cpp/instances/common/attention_unified_selectors.cpp (or document why 3D selector parity in C++ does not cover this function).
HIGH §D · dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:527 · Put the knob on the KernelSpec and delete the environment read.
HIGH §G · dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909 · Evaluate _enable_i64_kv_addr_3d, _tiled_3d_cache_key, _spec_generic_3d, and with_num_kv_blocks on both develop and the PR branch across a grid of (arch, kv_fp8, use_wide_kv_load, tile_size, head_size, cache_bytes) and attach the resulting differential table to the PR description.
MEDIUM §F · summary · Retitle as type(scope): summary, 10–80 characters, scope [a-z0-9-]+.

Needs info

§D.20 dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 modify the kernel-level 3D spec builder/selector, while the PR body states 'The C++ engine is untouched'; confirm whether the C++ selector/spec-builder has a 3D gfx942 path that needs mirroring or if 3D gfx942 spec building is Python-only.
§G.3 PR body reports running targeted library/dispatch pytest suites (with 1 pre-existing failure baselined on develop) and a 96-spec llvm22 IR identity check, but does not confirm running the full tools/run_checks.py gate sweep or platform/tests.

Section notes

§D: Items 1-11 of 21 in Section D
§D: Items 12-21 of Section D
§E: Clean, well-scoped library fix with proper layering, no dead parameters, and no policy violations.
§G: Graded items 1-17 of section G.
§G: Items 18–34 of 34
§H: Trace of bounds in this PR: (1) KV cache byte bound: extent source is num_kv_blocks * block_bytes (attention_unified.py:2932), compared against i32_kv_cache_bytes(...) (attention_tiled_3d.py:330), which matches the addressing range of the selected loader (0x8000_0000 for flat i32 byte-offset wide/fp8 loads when (tile_size * head_size) % (64 * 8) == 0, and 0x7FFF_0000 for async buffer copies). They agree because wide_kv_load_fits (attention_tiled_3d.py:325) is shared directly with the kernel builder (attention_tiled_3d.py:826). No device-side masks or indirection loops are modified.

Graded with the rocKE PR checklist, one model pass per section. FAIL rows that sit on a diff line are inline comments.

§A graded 14/14

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825 refactors WIDE_OK into wide_kv_load_fits without altering emitted IR or adding a new kernel family.
2	N/A	No core lowering-op or op-handler files (core/lower_*, core/ir) are modified in this PR.
3	FAIL	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 and dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 add _enable_i64_kv_addr_3d and gfx942_3d_kv_needs_i64_addr to Python selectors/spec-builder without mirroring the change in cpp/instances/common/attention_unified_selectors.cpp.
4	N/A	No C++ kernel emitter or IR-emitting code is modified in this PR.
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825 preserves identical IR emission and leaves representative-IR golden files untouched.
6	N/A	No IR changes are introduced and no golden files are cited as cross-engine parity proof.
7	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2939 guards the new 3D KV address check to arch == 'gfx942' and caches above the i32 buffer threshold, with no IR op changes on hot paths.
8	N/A	No C++ code is modified in this PR.
9	N/A	No shared op-handler fix or lowerer-only arch divergence is in this PR.
10	N/A	No new IR-emitting feature flag is introduced; use_i64_kv_addr remains refused on gfx942 3D.
11	N/A	No new IR op is added in this PR.
12	N/A	core/backend.py is not modified in this PR.
13	N/A	LLVM lowering and .ll emission are not modified in this PR.
14	N/A	No classic helper under helpers/ is modified in this PR.

§B graded 6/6

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330-341 classifies the per-loader i32 cache limits (`0x8000_0000` for flat i32 byte offset loads vs `0x7FFF_0000` for buffer resources), while keeping the >2 GiB refusal as `NotImplementedError` (tested at dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:556).
2	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1085-1092, and dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:322-329 all route gfx942 3D through `gfx942_3d_kv_needs_i64_addr` (defined in dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2932) so…
3	PASS	This PR restores 3D tiled decode coverage on gfx942 for 2 GiB KV caches (dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:546-552) rather_than demoting any shape, and oversized caches continue to raise `NotImplementedError` loudly.
4	PASS	No normalization or silent clamping is introduced; caches exceeding the loader's addressing limit set `use_i64_kv_addr=True` via `gfx942_3d_kv_needs_i64_addr` (dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2932) and are rejected by `UnifiedAttention3DTiledSpec` (dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-133).
5	PASS	The newly opened (0x7FFF0000, 0x80000000] range for wide/fp8 loaders on gfx942 3D is covered by unit tests in `TestGfx942Tiled3DKvAddr` (dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521-595) and `test_tuning_space.py` (dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:317-330), plus GPU validation at the 2^31-byte boundary noted in the PR test plan.
6	PASS	`i32_kv_cache_bytes` and `wide_kv_load_fits` in dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341 encode strictly functional hardware/instruction addressing invariants (signed 32-bit flat load offset vs buffer resource byte bound and wave lane divisibility).

§C graded 10/10

#	Verdict	Evidence
1	PASS	Extracted shared predicates `wide_kv_load_fits` and `i32_kv_cache_bytes` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325` and `gfx942_3d_kv_needs_i64_addr` / `_enable_i64_kv_addr_3d` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909`, plus `_kv_block_stride` in `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:134`.
2	N/A	No new kernel builder family or shape-class kernel is introduced in this PR.
3	PASS	New helper names describe the operation and hardware addressing rule (`wide_kv_load_fits`, `i32_kv_cache_bytes` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`, `gfx942_3d_kv_needs_i64_addr` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909`), not specific workload shapes.
4	PASS	The gfx942-specific loader limit calculation `i32_kv_cache_bytes` and `wide_kv_load_fits` live in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`, while `common/` holds the target-predicated selector wrappers (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935`).
5	PASS	All 7 modified files directly belong to the 3D attention KV-addressing rule across spec builder (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`), selector/cache key (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030`), dispatch tuning (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`), and their tests.
6	PASS	Factored the inline `WIDE_OK` check in `build_unified_attention_3d_tiled` into `wide_kv_load_fits(T, HD)` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:826`) as a byte-identical refactor so `i32_kv_cache_bytes` shares the exact same rule.
7	N/A	This PR is a targeted bugfix rather than a pure cleanup PR.
8	PASS	Reuses and composes with existing `_enable_i64_kv_addr`, `_kv_block_bytes`, and `kv_addr_width_for_builder` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2939`.
9	PASS	Updated every sibling site that computes `use_i64_kv_addr` for gfx942 3D: `_spec_generic_3d` (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`), `_tiled_3d_cache_key` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030`), `AttentionTuningSpec.with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`), and…
10	PASS	`_enable_i64_kv_addr_3d` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2939`) and `with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`) explicitly gate the loader-dependent limit on `arch == "gfx942"` (and `path == "3d"`), leaving gfx950/gfx1250 and 2D paths untouched, and updates the field comment in…

§D graded 21/21

#	Verdict	Evidence
1	FAIL	dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:527 reads the environment
2	N/A	This PR does not add or modify any `Capability` declarations or candidate `arches` lists.
3	N/A	This PR does not add or modify any candidate `_supports` or `admits` predicates.
4	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 (`_enable_i64_kv_addr_3d(problem: UnifiedAttentionProblem, arch: str)` takes `arch` explicitly from the caller rather than probing the host device).
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030 (`_tiled_3d_cache_key` uses `_enable_i64_kv_addr_3d(problem, arch)`, matching the `use_i64_kv_addr` predicate in `_spec_generic_3d` at `dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`).
6	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030, and dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1085 all route gfx942 3D `use_i64_kv_addr` through `gfx942_3d_kv_needs_i64_addr`.
7	N/A	This PR does not introduce or move hand-pinned overrides relative to machine-regenerable heuristics.
8	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341 (`wide_kv_load_fits` and `i32_kv_cache_bytes` define the single source of truth shared by the kernel builder at line 826 and `gfx942_3d_kv_needs_i64_addr` at `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2924`).
9	N/A	This PR does not register a new kernel or architecture candidate.
10	N/A	This PR does not add a new spec field or feature; it refines the threshold for the existing `use_i64_kv_addr` field on gfx942 3D.
11	N/A	This PR does not register, promote, or alter `opt_in` or `arches` for any candidate.
12	N/A	No candidate priority, candidate name, or custom ranker is added or modified in this PR.
13	N/A	This PR does not modify CandidateRegistry.select, pin handling, or add a wrapper/entry point around pin selection.
14	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030 updates _tiled_3d_cache_key to use _enable_i64_kv_addr_3d(problem, arch) so caches within the loader's i32 limit share a single cache key without per-shape recompilation, tested at dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:565.
15	N/A	No new candidate or arch module is added to the dispatcher registry in this PR.
16	N/A	No new operator family is introduced in this PR.
17	N/A	No new dispatcher candidate or cohort routing rule is added in this PR.
18	N/A	Registry ratchets (require_build, require_binding, require_torch_binding) and exempt sets are not touched in this PR.
19	PASS	Both the production spec builder/cache key (dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030) and the dispatcher explicit/tuning spec builders (dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1085…
20	NEEDS-INFO	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 modify the kernel-level 3D spec builder/selector, while the PR body states 'The C++ engine is untouched'; confirm whether the C++ selector/spec-builder has a 3D gfx942 path that needs mirroring or if 3D gfx942 spec building is Python-only.
21	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 fix the spec chooser (_enable_i64_kv_addr_3d) while leaving the kernel emitter in dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825 unchanged in behavior.

§E graded 17/17

#	Verdict	Evidence
1	PASS	All modified files are under `dnn-providers/hip-kernel-provider/rocke/library/` (e.g., `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`); no `platform/` files are touched.
2	PASS	No `import torch` was added in any modified file (e.g., `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:27`).
3	PASS	No torch dependency or ROCm library lookup via torch was added in the diff (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:27-46`).
4	PASS	Imports flow strictly downward: `builders` imports from `kernels` (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:35`), `dispatch` imports from `kernels` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:59`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:21`), and `kernels/common` imports within `kernels`…
5	N/A	No files under `platform/` or helper scripts were added or modified.
6	PASS	In `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825-826`, `WIDE_ELEMS` and `WIDE_OK` refactorings do not touch any IR value handles, preserving byte-identical emitted IR.
7	N/A	The PR fixes an i32 KV-cache byte-limit calculation for an existing loader without adding new env vars, dtypes, ops, kernel families, manifest kinds, or perf levers.
8	PASS	No Jira IDs, PR numbers, or usernames appear in code, comments, or tests (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-132`); the ticket ID `AICK-2716` is only in the PR body.
9	PASS	All changes across the 7 files are strictly scoped to bounding the gfx942 3D KV cache by its K/V loader (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948`).
10	PASS	Changes are small, localized additions without file moves or splits (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:320-342`).
11	PASS	Only deliverable library code and unit tests are committed (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521`).
12	PASS	This is an explicitly gfx942-specific 3D loader limit fix, gated by `arch == "gfx942"` while preserving existing behavior for other arches (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2939`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:321`).
13	N/A	No symbols or concepts were renamed or removed as dead code in this PR.
14	PASS	Removed lines in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-134` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:133-141` are intentional comment updates and helper extractions (`_kv_block_stride`), with no unintended loss of upstream code or notes.
15	PASS	Every parameter in the newly added functions (`wide_kv_load_fits`, `i32_kv_cache_bytes`, `gfx942_3d_kv_needs_i64_addr`, `_enable_i64_kv_addr_3d`, `_kv_block_stride`) is read and used in its function body (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948`…
16	N/A	This item applies to review-finding severity reporting and there are no failures to report in this section.
17	PASS	No performance claims or software-achieved performance numbers appear in the PR description or code diff (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-132`).

§F graded 11/11

#	Verdict	Evidence
1	PASS	Branch `users/dlangbe/rocke-gfx942-3d-kv-addr-limit` matches `users/<user>/...`; see `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`.
2	FAIL	title `fix(rocke/attention): bound gfx942 3D KV cache by its K/V loader` is 64 characters and does not match type(scope): summary with a 10–80 character length
3	PASS	description is at least 30 characters and contains an issue reference
4	PASS	test file `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py` is in the diff
5	PASS	Only Python source and test files are modified (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:35`), with no keys, certs, or secrets.
6	PASS	Diff hunks in all 7 Python files follow black formatting, e.g., `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:134`.
7	N/A	No review threads or bot findings are provided in the prompt context.
8	N/A	Base branch is `develop`, so this is not a stacked PR on a feature branch.
9	PASS	All call sites and tests are included in one cohesive change (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`).
10	PASS	Tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521` directly exercise the loader limit, 2 GiB boundary, cache key, and tuning spec behavior.
11	PASS	PR title and detailed body are populated in the PR metadata corresponding to changes in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330`.

§G graded 34/34

#	Verdict	Evidence
1	PASS	PR body and `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:546` do not rely on byte-identity for correctness; IR identity was checked alongside functional unit tests and on-silicon fp32 reference runs.
2	PASS	PR body Test Plan documents on-silicon gfx942 verification via `run_unified_attention_torch` against an fp32 torch reference at `2^31` bytes for the shapes tested in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:546`.
3	NEEDS-INFO	PR body reports running targeted library/dispatch pytest suites (with 1 pre-existing failure baselined on develop) and a 96-spec llvm22 IR identity check, but does not confirm running the full `tools/run_checks.py` gate sweep or `platform/tests`.
4	PASS	`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:546` (`test_exactly_2gib_decode_builds_on_wide_loader`, `test_3d_key_follows_loader_limit`, `test_explicit_3d_spec_and_bind_follow_loader_limit`) and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:324` fail before the change (verified by mutation check in PR body).
5	PASS	`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:532` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320` test each modified entry point (`i32_kv_cache_bytes`, `_tiled_3d_spec_from_problem`, `_tiled_3d_cache_key`, `make_explicit_attention_3d_specs`, `with_num_kv_blocks`) with reachable decode problem shapes and pin both acceptance at 2 GiB and refusal past the…
6	PASS	Comments and docstrings in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330` and `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909` match the `0x8000_0000` vs `0x7FFF_0000` branch logic and are directly asserted in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:532`.
7	N/A	This PR does not add or modify a design document.
8	N/A	This PR does not modify test harnesses or dtype fallback behavior.
9	N/A	This PR does not make LDS or occupancy claims.
10	N/A	This PR is a functional addressing-bound fix and makes no performance claims.
11	PASS	All Python routing, cache key, spec builder, and tuning spec surfaces are updated together in `dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`, and…
12	PASS	All callers determining `use_i64_kv_addr` for gfx942 3D (`_spec_generic_3d`, `_tiled_3d_cache_key`, `AttentionTuningSpec.with_num_kv_blocks`, `make_explicit_attention_3d_specs`) are updated in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`.
13	N/A	This PR does not touch LLVM intrinsics or `.td` files.
14	N/A	This PR does not classify hardware performance bottlenecks.
15	N/A	The PR diff is provided directly in the review prompt.
16	PASS	`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825` factors the existing `WIDE_OK` check into `wide_kv_load_fits` and reuses it across the kernel builder and `i32_kv_cache_bytes`.
17	N/A	This PR does not add or modify standalone scripts.
18	PASS	The KV-addressing refusal guard is proved to fire past 2 GiB on the wide loader and at 2 GiB on the async loader (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:554-564`) and to pass when safe (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:546-552`, `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:324-330`).
19	PASS	The test fixture uses `_AT_2GIB = 131072` (between `0x7FFF0000` and `0x80000000` bytes) to distinguish wide vs async loader limits across all gates: spec builder, cache key, `make_explicit_attention_3d_specs`, and `with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:501-596`).
20	N/A	The PR does not add or modify a text detector or linter for banned claims.
21	N/A	The PR does not add or modify any performance measurement or benchmarking harness code.
22	PASS	The added unit tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521-596` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320-330` run directly on CPU without skip guards or golden error entries.
23	N/A	The PR fixes a KV-cache size refusal boundary on gfx942 3D and makes no performance or speedup claims.
24	N/A	The PR does not re-bless or touch any golden IR fixtures.
25	N/A	The PR does not contain a codegen micro-optimization; emitted kernel IR is unchanged.
26	N/A	The PR is a correctness fix for KV-cache bounds and does not report benchmark comparisons.
27	N/A	The PR does not present a performance or routing A/B experiment.
28	N/A	The PR does not present counterfactual performance comparisons.
29	N/A	The PR does not swap any guarded math primitives for fast approximations.
30	N/A	The PR does not make register-spill or scratch-memory claims.
31	PASS	The PR description and mutation check verify the baseline defect on `develop` (`_enable_i64_kv_addr` rejecting 2 GiB caches on gfx942 3D in `dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:399`).
32	N/A	The PR does not report performance, VGPR, or spill measurements.
33	FAIL	`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948` and `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341` introduce pure decision functions (`_enable_i64_kv_addr_3d`, `gfx942_3d_kv_needs_i64_addr`, `i32_kv_cache_bytes`), and the PR body states behavior across arches/loaders in prose without attaching a differential evaluation table across the input domain (arches, dtypes, head_size, tile_size, block_size, num_kv_blocks) and downstream consumers (spec builder, cache key, `with_num_kv_blocks`).
34	N/A	The PR does not add or modify an opt-in kernel output flag.

§H graded 5/5

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909 validate `num_kv_blocks * block_bytes` against the loader-specific limit (`0x8000_0000` for flat global loads vs `0x7FFF_0000` for buffer-resource loads) before spec/kernel build.
2	N/A	This PR does not add or modify device-side table lookups or indirection value handling.
3	N/A	This PR does not add or modify device-side hot-loop `div`/`mod` operations.
4	N/A	This PR does not add or modify device-side masks or bounds derived from runtime sequence lengths (`kv_lens`, `cu_seqlens`).
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:554 and dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:326 provide negative tests verifying `NotImplementedError` when `num_kv_blocks` exceeds the respective wide-load (`2^31`) or async buffer-load (`0x7FFF0000`) bounds.

§I graded 6/6

#	Verdict	Evidence
1	N/A	This PR refines the i32 KV-cache byte limit for the gfx942 3D tiled attention kernel and does not add or modify performance benchmarks or routing selection measurements.
2	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-133 and dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:554-563 keep valid caches up to 2^31 bytes on the flat/wide loader and loudly reject oversized caches with NotImplementedError instead of silently misreading or failing cryptically.
3	PASS	dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521-596 and dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320-330 cover both the default selector path and explicit tuning-space candidates across wide, fp8, and async loader boundaries.
4	N/A	This PR does not add or modify performance reporting tables or benchmark columns.
5	N/A	This PR does not add or update baked tuning search snapshots.
6	N/A	This PR does not introduce or modify any DSL ops or hardware-instruction-named primitives.

§J graded 7/7

#	Verdict	Evidence
1	N/A	The diff contains no Markdown design or algorithm documents.
2	N/A	The diff contains no Markdown design or algorithm documents.
3	N/A	The diff contains no Markdown design or algorithm documents.
4	N/A	The diff contains no Markdown design or algorithm documents.
5	N/A	The diff contains no Markdown design or algorithm documents or complexity claims.
6	N/A	The diff contains no Markdown design or algorithm documents.
7	N/A	The diff adds no new Markdown documentation files.

§K graded 13/13

#	Verdict	Evidence
1	N/A	The diff does not add or modify any candidate definitions or `KnobSpace` subclasses.
2	N/A	No kernel spec fields or `KnobAxis` declarations are added, removed, or reclassified.
3	PASS	`use_i64_kv_addr` is a problem/runtime field specialized in `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:321` without changing what any `config_key` or `tuning_id` names (verified in `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320`).
4	N/A	The diff does not touch `KnobSpace.defaults()` or `KnobSpace.recorded()`.
5	N/A	The diff does not modify knob drop, inertness, or refusal rules in a `KnobSpace`.
6	PASS	Policy-free construction in `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:321` computes `use_i64_kv_addr` via the pure rule `gfx942_3d_kv_needs_i64_addr` using the explicit `knobs` and `tile` rather than calling production selector heuristics `_enable_i64_kv_addr_3d` or `_enable_gfx942_3d_wide_kv_load`.
7	N/A	The diff does not touch `KnobSpace.base(req)` or request normalization.
8	N/A	The diff does not touch knob value normalization or axis type coercion.
9	N/A	The diff does not touch benchmark replay, `spec_hash` verification, or `PinRefused` handling.
10	N/A	The diff does not touch `KnobSpace.find` or bare `tuning_id` resolution.
11	N/A	The diff does not touch sweep entry points or harness loops.
12	N/A	The diff does not reorder production stacks, change `accept_default`, or alter `auto` selection.
13	N/A	The diff does not touch benchmark harnesses or claim that sweeps drive `auto` selection.

§L graded 10/10

#	Verdict	Evidence
1	N/A	The diff does not add or modify a gfx target or touch arch_specs.json / C++ arch data.
2	N/A	The diff does not add or modify any MMA op_id or fragment layout maps.
3	N/A	The diff does not touch MMA selection, MfmaAtom catalogs, or MMA lowering.
4	N/A	The diff only factors out an existing gfx942-specific wide KV load divisibility check in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325` and does not touch platform wave_size…
5	N/A	The diff does not introduce cross-arch recipe sharing, transpose-LDS reads, K-packed atoms, or AsyncTileLoader changes.
6	N/A	The diff only modifies files under `library/` and does not touch `ArchTarget`, `core/arch/`, or `python/rocke/`.
7	N/A	The diff does not add or change logical dtypes, bit packing, instruction fragments, or FP8 dialect rules.
8	N/A	The diff does not touch scaled-MMA contracts or WMMA/MFMA scaled emission.
9	N/A	The diff does not add a new architecture target.
10	N/A	The diff does not touch intrinsic arch-domain artifacts or LLVM flavor membership lists.

§M graded 10/10

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825-827 uses pure host-time integers (T, HD, THREADS, WIDE_ELEMS) via wide_kv_load_fits(T, HD) without branching on SSA Values.
2	N/A	The diff does not touch legalize_for_target or any target legalization pass.
3	N/A	The diff does not touch IR printing or ck.dsl.ir/v1 serialization.
4	N/A	The diff does not touch portable IR schemas, importers, recorders, or magic division helpers.
5	N/A	The diff does not modify AsyncTileLoader usage or LDS layout/wait emissions.
6	N/A	The diff does not emit barriers, device memory loads, selects, or cross-lane shuffles.
7	N/A	The diff does not touch buffer resource word 3 or temporal cache hints.
8	N/A	The diff does not add intrinsic declarations or modify lowering engine selection.
9	N/A	The diff does not touch C++ public entry points or headers under cpp/include/rocke/.
10	N/A	The diff does not touch debug info emission or DWARF consumers.

§N graded 18/18

#	Verdict	Evidence
1	N/A	No helpers are added or promoted to platform/python/rocke/helpers/ in this diff.
2	N/A	The diff only refactors an existing integer divisibility check into wide_kv_load_fits and does not modify MFMA mapping, TensorView addressing, loaders, epilogues, or pipelines.
3	N/A	No SoftwarePipeline usage or configuration is added or modified in this diff.
4	N/A	No fused kernels, EpilogueOp definitions, or fusion schedules are touched in this diff.
5	N/A	No public or private APIs in rocke.helpers.tiling are added or changed in this diff.
6	N/A	No front-door/toolbox tiling helpers or LayoutStyle classes are added or modified in this diff.
7	N/A	No tiling layout overrides, accumulator descriptors, or MMA issue gates are modified in this diff.
8	N/A	No tiling memory primitives (lds_tile_alloc, lds_store, lds_read, or tiling global loads) are used or modified in this diff.
9	N/A	No N-D tensor axis roles, batch reductions, or FlowStage label transforms in helpers/tiling are touched in this diff.
10	N/A	No changes are made to tiling emit, LDS staging, or MMA issue in helpers/tiling.
11	N/A	No TileMma, Tiling, lds_swizzle, or derive_sched_group_counts APIs are used or changed in this diff.
12	N/A	The PR makes no LDS bank-conflict or memory coalescing claims and does not touch tiling analysis tools.
13	N/A	No WarpDistributionEncoding, make_tile_desc, or RegisterMapper code is used or modified in this diff.
14	N/A	No tiling verbs, LDS barriers, or pipeline variants are added or modified in this diff.
15	N/A	No tiling descriptor allocation or swizzled/padded bounds checks are added or modified in this diff.
16	N/A	No layout_optimizer, recommend(), or evaluate_transform calls are touched in this diff.
17	N/A	No changes are made to tiling_recorder, roundtrip analysis, or tiling visualization.
18	N/A	No InterleavedStyle layouts, tiling demo kernels, or tiling numeric gates are touched in this diff.

§O graded 16/16

#	Verdict	Evidence
1	N/A	The diff only touches `library/` attention files and does not modify IR verification, address spaces, or required attributes in `platform/`.
2	N/A	The diff does not emit or modify `scf.for` regions, terminators, or block emission in `platform/`.
3	N/A	The diff does not touch IR emission, SSA naming, intrinsic tables, or metadata slots in `platform/`.
4	N/A	The diff does not modify IR type definitions, `SmemType`, or IR parsing in `platform/`.
5	N/A	The diff does not touch `core/passes.py`, `cpp/core/passes.cpp`, or op purity tables.
6	N/A	The diff does not touch constant folding passes in Python or C++.
7	N/A	The diff does not modify kernel attributes, codegen policy, or COMGR options in `platform/`.
8	N/A	The diff does not set or modify `CodegenPolicy` or `SchedulerStrategy`.
9	N/A	The diff does not modify waitcnt encoding or barrier lowering in `platform/`.
10	N/A	The diff does not touch LLVM lowerers or parameter attribute handling in `platform/`.
11	N/A	The diff does not touch `platform/` core internals or `ArchTarget` definitions.
12	N/A	The diff does not touch `platform/` core internals or target catalog width/size caps.
13	N/A	The diff does not touch any public C structs, enums, or ABI versions under `cpp/include/rocke/`.
14	N/A	The diff does not touch any C++ files, headers, bindings, or CMake files.
15	N/A	The diff does not touch C++ engine fallback logic, LLVM flavor resolution, or lowering backends.
16	N/A	The diff does not touch C++ library codegen or `known_gaps.md` areas in `platform/`.

§P graded 14/14

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:344 keeps build_unified_attention_3d_tiled(spec, *, arch='gfx942') with use_i64_kv_addr as a defaulted field on UnifiedAttention3DTiledSpec at line 133.
2	N/A	The diff does not touch kernarg signatures, argument packing, GEMM, or convolution ABIs.
3	N/A	The diff does not touch launch grid geometry or GEMM/convolution launch sizing.
4	N/A	The diff does not touch LDS capacity gates or LDS buffer allocation.
5	N/A	The diff does not touch WMMA/RDNA GEMM, wave_size reductions, or multi-D/multi-ABD GEMM instances.
6	N/A	The diff does not touch Stream-K, MoE sorting, fused MoE, or split-K workspaces.
7	N/A	The diff does not touch Stream-K, persistent GEMM, GroupedGemmLauncher, or SUPPORT_MATRIX.md.
8	N/A	The diff does not touch quantization helpers or MX GEMM scale decoding.
9	N/A	The diff does not introduce or modify numeric emulation or floating-point decode math.
10	N/A	The diff does not touch manifest emitters, manifest schemas, or run_manifest.
11	N/A	The diff does not touch runtime kernel launchers, stream synchronization, or WorkspacePool.
12	N/A	The diff does not touch COMGR or HIP library loading.
13	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4030 updates _tiled_3d_cache_key and admission logic via _enable_i64_kv_addr_3d, tested in dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:565 and verified with gfx942 GPU numeric tests in the PR test plan.
14	N/A	The diff does not touch examples, expected.json files, platform instances, or helpers/.

§Q graded 7/7

#	Verdict	Evidence
1	N/A	This PR only adds test methods to existing `rocke/library/tests/` files and adds or removes no test files or `platform/` tests.
2	N/A	This PR does not introduce a new kernel family or variant; it adjusts the i32 KV-cache byte limit selector logic for the existing gfx942 tiled 3D kernel.
3	N/A	This PR does not modify or rely on platform differential gates alone; numerics on gfx942 and unit tests are provided for a library selector change whose emitted IR is unchanged.
4	N/A	No goldens are re-blessed and the valid spec space in the lowerer or builder is not widened (`use_i64_kv_addr` remains rejected by `UnifiedAttention3DTiledSpec`).
5	PASS	New tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521-596` mock the architecture (`_patch_arch("gfx942")`) and clean up environment variables (`mock.patch.dict(os.environ)`) so they run portably on CPU without a GPU or torch.
6	N/A	This PR does not refactor any gate or test harness.
7	N/A	This PR modifies Python library spec-selection thresholds rather than the platform C++/Python backend rejection contract.

§R graded 11/11

#	Verdict	Evidence
1	N/A	The diff introduces no new kernel body, algorithm, tiling strategy, pipeline variant, or structural performance claim, only a capacity-limit check for gfx942 3D KV addressing.
2	N/A	The diff modifies no performance lever in the kernel builder or heuristic defaults.
3	N/A	The diff touches no GEMM, LDS, prefetch, ISA, or launch-shape optimization lever.
4	N/A	Emitted kernel IR and ISA are unchanged by this PR; no performance primitive was modified.
5	N/A	The diff adds or changes no global memory access in any kernel body (only extracts wide_kv_load_fits as a helper).
6	N/A	The diff makes no LDS or MMA layout changes.
7	N/A	The PR makes no bottleneck claim or performance optimization change.
8	N/A	The diff changes no waits, barriers, or scheduling hints.
9	N/A	The PR fixes a functional NotImplementedError regression at 2 GiB KV cache size, not a performance regression or shape-trading lever.
10	N/A	The diff makes no codegen, occupancy, or benchmark claims.
11	N/A	The PR is a bug fix for KV cache capacity bounds and introduces no new optimization lesson, probe, or analysis tool.

§S graded 8/8

#	Verdict	Evidence
1	N/A	The diff does not add any public symbol to the `rocke` platform package (`rocke`, `rocke.core`, `rocke.runtime`, `rocke.analysis`, `rocke.helpers`, `rocke.instances`, `rocke.dispatch`) or any `rocke_*` C entry point…
2	PASS	The behavior update to `AttentionTuningSpec.with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`) and `make_explicit_attention_3d_specs` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:320`) updates the existing test in `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320` to check both wide and non-wide loaders…
3	N/A	The diff does not remove or rename any public API.
4	N/A	The diff does not touch any `__all__` list or add symbols to platform package roots.
5	PASS	The tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:532` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:324` assert exact byte limits (`2**31` and `0x7FFF0000`), spec field values (`use_wide_kv_load`, `use_i64_kv_addr`), cache-key equality/inequality, and negative `NotImplementedError` raises one block past the loader limit.
6	PASS	All new and updated spec-building, cache-key, and tuning-spec limit checks run on CPU in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:521` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:317` without requiring a GPU or torch.
7	N/A	The diff only touches the Python-only gfx942 3D attention kernel (`attention_tiled_3d.py`) and library dispatch/selector helpers, which have no C++ twin or C ABI binding.
8	N/A	The diff touches only `rocke/library/` and does not modify `rocke/platform/` code, manifests, runtime, or any API used in `rocke/platform/python/rocke/README.md`.

The 3D segment spec picks its KV addressing from problem.num_kv_blocks, which a caller can leave stale. Now that the gfx942 wide and fp8 loaders read caches up to 2^31 bytes, a stale count on a larger cache would read a wrapped address instead of zeros. _run_3d_tiled_on_stream now checks the real K cache against the segment kernel's limit before the eager and graph launches, as the 2D path already does. Strided K/V and gfx1250 are not checked. Also from review: use _kv_block_bytes in the explicit 3D tuning spec, and drop the environment override from the async-loader test (head size 256 selects the async copies). Co-Authored-By: Claude <noreply@anthropic.com>

dlangbe · 2026-10-23T19:37:40Z

@yraparti
§F: retitled to fix(rocke): bound gfx942 3D KV cache by its K/V loader.
§G.3: full library/tests on CPU added to the test plan. platform/ is untouched; the byte-identity gate was not rerun because no C++ or emitted IR changes (IR identity checked on 96 specs).

yraparti

rocKE checklist re-review of the fixes since `c9c73c2a8e85`

ROCm/rocm-libraries#14216 · 6120fae1db06 · model gemini-4-argon, fallback gpt-5.5

PASS · graded 238/238 · BLOCKER 0, HIGH 1, MEDIUM 0, LOW 0, NEEDS-INFO 2

Since the last review (`c9c73c2a8e85`)

Resolved 3 · still open 1 · new 0

✅ §D.1 was FAIL, now PASS — had asked: Put the knob on the KernelSpec and delete the environment read.
✅ §F.2 was FAIL, now PASS — had asked: Retitle as type(scope): summary, 10–80 characters, scope [a-z0-9-]+.
✅ §G.33 was FAIL, now PASS — had asked: Evaluate _enable_i64_kv_addr_3d, _tiled_3d_cache_key, _spec_generic_3d, and with_num_kv_blocks on both develop and the PR branch across a grid of (arch, kv_fp8, use_wide_kv_load, tile_size, head_size, cache_bytes) and attach the resulting differential table to the PR description.
⏳ §A.3 still FAIL (HIGH): Mirror gfx942_3d_kv_needs_i64_addr and _enable_i64_kv_addr_3d in cpp/instances/common/attention_unified_selectors.cpp (or document why C++ selector parity does not cover 3D i64 KV address selection).

Findings

HIGH §A · dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 · Mirror gfx942_3d_kv_needs_i64_addr and _enable_i64_kv_addr_3d in cpp/instances/common/attention_unified_selectors.cpp (or document why C++ selector parity does not cover 3D i64 KV address selection).

Needs info

§D.20 New commits did not address this item: dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 modify the kernel-level 3D spec builder/selector while the PR body states 'The C++ engine is untouched'; confirm whether the C++ selector/spec-builder has a 3D gfx942 path that needs mirroring or if 3D gfx942 spec building is Python-only.
§G.3 Since the previous review, the PR body updated the Test Plan to report running the full library/tests suite on CPU (with 30 failures baselined against a04f810197d5) and a 96-spec llvm22 IR identity check, but it still notes the byte-identity gate was not rerun and does not confirm running tools/run_checks.py or platform/tests.

Section notes

§A: Re-reviewed head 6120fae against c9c73c2. Item 3 remains FAIL because the new commits only add 3D launch-guard and test updates in Python without updating cpp/instances/common/attention_unified_selectors.cpp.
§D: Re-review of commits c9c73c2..6120fae: the environment read in test_selector_parity.py was removed and replaced with shape-driven spec selection.
§D: Items 12-21 of Section D re-reviewed against 6120fae.
§G: Items 1–17 of 34 (re-review of head 6120fae)
§G: Re-review of items 18-34. Item 33 (previously FAIL) is resolved by the differential table added to the PR description covering 288 cases across gfx942/gfx950, loader kinds, head/block sizes, and downstream consumers. New 3D launch guard and tests in test_selector_parity.py also pass.
§H: Trace: (1) gfx942 3D paged KV cache addressing bound — extent source is i32_kv_cache_bytes (0x8000_0000 for fp8 or wide global load when wide_kv_load_fits(tile_size, head_size), else 0x7FFF_0000 for async buffer load); compile-time/launch range visited is num_kv_blocks * block_bytes (spec) and actual k tensor size (_check_kv_addr_width in _run_3d_tiled_on_stream); they agree because both spec builders and the 3D launch guard enforce <= i32_kv_cache_bytes(...). (2) gfx950 3D paged KV cache addressing bound — extent source is _spec_kv_addr_limit (0x7FFF_0000 when use_i64_kv_addr=False, unlimited when True); launch tensor k is checked against _3d_spec_kv_addr_limit in _run_3d_tiled_on_stream; they agree.

Graded with the rocKE PR checklist, one model pass per section. FAIL rows that sit on a diff line are inline comments.

§A graded 14/14

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:826 refactors WIDE_OK into wide_kv_load_fits without altering emitted IR or adding a new kernel family.
2	N/A	No core lowering-op or op-handler files (core/lower_*, core/ir) are modified in this PR.
3	FAIL	Unresolved since previous review: dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 and dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 add _enable_i64_kv_addr_3d and gfx942_3d_kv_needs_i64_addr to Python selectors and the 3D spec builder without mirroring them in cpp/instances/common/attention_unified_selectors.cpp.
4	N/A	No C++ kernel emitter or IR-emitting code is modified in this PR.
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:826 preserves identical IR emission and leaves representative-IR golden files untouched.
6	N/A	No IR changes are introduced and no golden files are cited as cross-engine parity proof.
7	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2939 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4437 guard the 3D KV address selection and memoized launch check without adding ops on any IR hot path.
8	N/A	No C++ code is modified in this PR.
9	N/A	No shared op-handler fix or lowerer-only arch divergence is in this PR.
10	N/A	No new IR-emitting feature flag is introduced; use_i64_kv_addr remains refused on gfx942 3D.
11	N/A	No new IR op is added in this PR.
12	N/A	core/backend.py is not modified in this PR.
13	N/A	LLVM lowering and .ll emission are not modified in this PR.
14	N/A	No classic helper under helpers/ is modified in this PR.

§B graded 6/6

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330-341 classifies the per-loader i32 cache limits (`0x8000_0000` for flat i32 byte offset loads vs `0x7FFF_0000` for buffer resources), and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049-3066 records `_KV_LIMIT_NO_I64_PATH` for the launch guard while keeping the >2 GiB spec refusal as `NotImplementedError` (tested at…
2	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082-1092, and dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:312-320 all route gfx942 3D through `gfx942_3d_kv_needs_i64_addr` (defined in dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2932), and…
3	PASS	This PR restores 3D tiled decode coverage on gfx942 for 2 GiB KV caches (dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:568-574) rather than demoting any shape, and oversized caches raise `NotImplementedError` or `ValueError` loudly (dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:576-633).
4	PASS	No normalization or silent clamping is introduced; caches exceeding the loader's addressing limit set `use_i64_kv_addr=True` via `gfx942_3d_kv_needs_i64_addr` (dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2932) and are rejected by `UnifiedAttention3DTiledSpec`, while callers passing a stale `num_kv_blocks` at launch are rejected by `_check_kv_addr_width` in `_run_3d_tiled_on_stream`…
5	PASS	The newly opened (0x7FFF0000, 0x80000000] range for wide/fp8 loaders on gfx942 3D and the new 3D launch guard on gfx942/gfx950 are covered by unit tests in `TestGfx942Tiled3DKvAddr` (dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:549-655) and `test_tuning_space.py` (dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320-330).
6	PASS	`i32_kv_cache_bytes` and `wide_kv_load_fits` in dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341 encode strictly functional hardware/instruction addressing invariants (signed 32-bit flat load offset vs buffer resource byte bound and wave lane divisibility).

§C graded 10/10

#	Verdict	Evidence
1	PASS	Extracted shared predicates `wide_kv_load_fits` and `i32_kv_cache_bytes` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`, `gfx942_3d_kv_needs_i64_addr`, `_enable_i64_kv_addr_3d`, and `_3d_spec_kv_addr_limit` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909`, and reused `_kv_block_bytes` in…
2	N/A	No new kernel builder family or shape-class kernel is introduced in this PR.
3	PASS	New helper names describe the operation and hardware addressing rule (`wide_kv_load_fits`, `i32_kv_cache_bytes` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`, `gfx942_3d_kv_needs_i64_addr` and `_3d_spec_kv_addr_limit` in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909`), not specific workload shapes.
4	PASS	The gfx942-specific loader limit calculation `i32_kv_cache_bytes` and `wide_kv_load_fits` live in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`, while `common/` holds the target-predicated selector and launch-limit wrappers (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935`).
5	PASS	All 7 modified files directly belong to the 3D attention KV-addressing rule across spec builder (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`), selector/cache key and launch guard (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050`), dispatch tuning (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`), and their tests.
6	PASS	Factored the inline `WIDE_OK` check in `build_unified_attention_3d_tiled` into `wide_kv_load_fits(T, HD)` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:826`) as a byte-identical refactor so `i32_kv_cache_bytes` shares the exact same rule.
7	N/A	This PR is a targeted bugfix rather than a pure cleanup PR.
8	PASS	Reuses and composes with existing `_enable_i64_kv_addr`, `_kv_block_bytes` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:17`), `kv_addr_width_for_builder`, and `_check_kv_addr_width` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4447`).
9	PASS	Updated every sibling site that decides or checks `use_i64_kv_addr` for 3D attention: `_spec_generic_3d` (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`), `_tiled_3d_cache_key` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050`), `_run_3d_tiled_on_stream` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4437`)…
10	PASS	`_enable_i64_kv_addr_3d` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935`), `_3d_spec_kv_addr_limit` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049`), and `with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`) explicitly gate the loader-dependent limit on `arch == "gfx942"`, while updating the shared…

§D graded 21/21

#	Verdict	Evidence
1	PASS	Resolved since previous review: the os.environ manipulation in test_selector_parity.py was removed, and test_async_loader_bounded_by_buffer_range at dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:581 now exercises the async loader via problem shape (head_size=256) and explicit spec fields (dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:128-133).
2	N/A	This PR does not add or modify any Capability declarations or candidate arches lists.
3	N/A	This PR does not add or modify any candidate _supports or admits predicates.
4	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 (_enable_i64_kv_addr_3d(problem: UnifiedAttentionProblem, arch: str) takes arch explicitly from the caller rather than probing the host device).
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050 (_tiled_3d_cache_key uses _enable_i64_kv_addr_3d(problem, arch), matching the use_i64_kv_addr predicate in _spec_generic_3d at dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400).
6	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050 and 4444, and dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1085 keep the spec builder, 3D cache key, 3D launch guard (_3d_spec_kv_addr_limit), and tuning spec in agreement via i32_kv_cache_bytes and gfx942_3d_kv_needs_i64_addr.
7	N/A	This PR does not introduce or move hand-pinned overrides relative to machine-regenerable heuristics.
8	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341 (wide_kv_load_fits and i32_kv_cache_bytes define the single source of truth shared by the kernel builder at line 826, gfx942_3d_kv_needs_i64_addr at dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2924, and _3d_spec_kv_addr_limit at line 3055).
9	N/A	This PR does not register a new kernel or architecture candidate.
10	N/A	This PR does not add a new spec field or feature; it refines the threshold for the existing use_i64_kv_addr field on gfx942 3D.
11	N/A	This PR does not register, promote, or alter opt_in or arches for any candidate.
12	N/A	No candidate priority, candidate name, or custom ranker is added or modified in this PR.
13	N/A	This PR does not modify CandidateRegistry.select, pin handling, or add a wrapper/entry point around pin selection.
14	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050 updates _tiled_3d_cache_key to use _enable_i64_kv_addr_3d(problem, arch) and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4438 memoizes _3D_KV_ADDR_LIMITS per cache_key so caches within the loader's i32 limit share a single cache key without per-shape recompilation, tested at…
15	N/A	No new candidate or arch module is added to the dispatcher registry in this PR.
16	N/A	No new operator family is introduced in this PR.
17	N/A	No new dispatcher candidate or cohort routing rule is added in this PR.
18	N/A	Registry ratchets (require_build, require_binding, require_torch_binding) and exempt sets are not touched in this PR.
19	PASS	Both the production spec builder/cache key/launch path (dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4438) and the dispatcher explicit/tuning spec builders…
20	NEEDS-INFO	New commits did not address this item: dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 modify the kernel-level 3D spec builder/selector while the PR body states 'The C++ engine is untouched'; confirm whether the C++ selector/spec-builder has a 3D gfx942 path that needs mirroring or if 3D gfx942 spec building is Python-only.
21	PASS	dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935 fix the spec chooser (_enable_i64_kv_addr_3d) while leaving the kernel emitter in dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825 unchanged in behavior.

§E graded 17/17

#	Verdict	Evidence
1	PASS	All modified files are under `dnn-providers/hip-kernel-provider/rocke/library/` (e.g., `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`); no `platform/` files are touched.
2	PASS	No `import torch` was added in any modified file (e.g., `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:33-46`).
3	PASS	No torch dependency or ROCm library lookup via torch was added in the diff (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:33-46`).
4	PASS	Imports flow strictly downward: `builders` imports from `kernels` (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:35`), `dispatch` imports from `kernels` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:59`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:17-22`), and `kernels/common` imports within `kernels`…
5	N/A	No files under `platform/` or helper scripts were added or modified.
6	PASS	In `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825-826`, `WIDE_ELEMS` and `WIDE_OK` refactorings do not touch any IR value handles, preserving byte-identical emitted IR.
7	N/A	The PR fixes an i32 KV-cache byte-limit calculation and 3D launch guard for existing loaders without adding new env vars, dtypes, ops, kernel families, manifest kinds, or perf levers.
8	PASS	No Jira IDs, PR numbers, or usernames appear in code, comments, or tests (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-132`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049-3078`); the ticket ID `AICK-2716` is only in the PR body.
9	PASS	All changes across the 7 files are strictly scoped to bounding the 3D KV cache by its K/V loader and guarding the 3D launch path (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4435-4447`).
10	PASS	Changes are small, localized additions without file moves or splits (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:320-342`).
11	PASS	Only deliverable library code and unit tests are committed (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:549`).
12	PASS	Both gfx942 and gfx950 are covered in the 3D launch guard and tests while gfx1250 is explicitly scoped out (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3054-3066`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4436-4437`, `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:609-633`).
13	N/A	No upstream symbols or concepts were renamed or removed as dead code in this PR.
14	PASS	Removed lines in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-134`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:138-143`, and `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3075-3077` are intentional comment updates and deduplication with `_kv_block_bytes`, with no unintended loss of upstream code or notes.
15	PASS	Every parameter in the newly added functions (`wide_kv_load_fits`, `i32_kv_cache_bytes`, `gfx942_3d_kv_needs_i64_addr`, `_enable_i64_kv_addr_3d`, `_3d_spec_kv_addr_limit`, `_decode_prob`, `_launch_3d`) is read and used in its function body (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325-341`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948`…
16	N/A	This item applies to review-finding severity reporting and there are no failures to report in this section.
17	PASS	No performance claims or software-achieved performance numbers appear in the PR description or code diff (`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-132`).

§F graded 11/11

#	Verdict	Evidence
1	PASS	Branch `users/dlangbe/rocke-gfx942-3d-kv-addr-limit` matches `users/<user>/...`; see `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325`.
2	PASS	title `fix(rocke): bound gfx942 3D KV cache by its K/V loader` matches type(scope): summary and is 54 characters
3	PASS	description is at least 30 characters and contains an issue reference
4	PASS	test file `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py` is in the diff
5	PASS	Only Python source and test files are modified (`dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:35`), with no keys, certs, or secrets.
6	PASS	Diff hunks in all 7 Python files follow black formatting, including the new changes in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049` and `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:524`.
7	N/A	No review threads or bot findings are provided in the prompt context.
8	N/A	Base branch is `develop`, so this is not a stacked PR on a feature branch.
9	PASS	All call sites, launch guards, and tests are included in one cohesive change (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4437`).
10	PASS	Tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:554` and `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:609` directly exercise the loader limit, 2 GiB boundary, cache key, 3D launch guard, and tuning spec behavior.
11	PASS	PR title and updated body (including the new 3D launch guard notes) are populated in the PR metadata corresponding to changes in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049`.

§G graded 34/34

#	Verdict	Evidence
1	PASS	PR body and `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:568` do not rely on byte-identity for correctness; IR identity was checked alongside functional unit tests and on-silicon fp32 reference runs.
2	PASS	PR body Test Plan documents on-silicon gfx942 verification via `run_unified_attention_torch` against an fp32 torch reference at `2^31` bytes (including with stale `num_kv_blocks=1024`) for the shapes tested in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:568` and `:609`.
3	NEEDS-INFO	Since the previous review, the PR body updated the Test Plan to report running the full `library/tests` suite on CPU (with 30 failures baselined against `a04f810197d5`) and a 96-spec llvm22 IR identity check, but it still notes the byte-identity gate was not rerun and does not confirm running `tools/run_checks.py` or `platform/tests`.
4	PASS	`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:568` (`test_exactly_2gib_decode_builds_on_wide_loader`, `test_3d_key_follows_loader_limit`, `test_3d_launch_checks_the_real_cache`, `test_gfx950_3d_launch_checks_the_real_cache`, `test_explicit_3d_spec_and_bind_follow_loader_limit`) and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:324` fail before the change (verified…
5	PASS	`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:555` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320` test each modified entry point (`i32_kv_cache_bytes`, `_tiled_3d_spec_from_problem`, `_tiled_3d_cache_key`, `_run_3d_tiled_on_stream`, `make_explicit_attention_3d_specs`, `with_num_kv_blocks`) with reachable decode problem shapes and pin both acceptance and…
6	PASS	Comments, docstrings, and PR prose match the branch logic in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:3049`, and `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4435`, and are directly asserted in…
7	N/A	This PR does not add or modify a design document.
8	N/A	This PR does not modify test harnesses or dtype fallback behavior.
9	N/A	This PR does not make LDS or occupancy claims.
10	N/A	This PR is a functional addressing-bound fix and makes no performance claims.
11	PASS	All Python routing, cache key, launch guard, spec builder, and tuning spec surfaces are updated together in `dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`, `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050` and `:4437`, `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`, and…
12	PASS	All callers determining or checking `use_i64_kv_addr` for 3D (`_spec_generic_3d`, `_tiled_3d_cache_key`, `_run_3d_tiled_on_stream`, `AttentionTuningSpec.with_num_kv_blocks`, `make_explicit_attention_3d_specs`) are updated in `dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2935` and `:4437` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`.
13	N/A	This PR does not touch LLVM intrinsics or `.td` files.
14	N/A	This PR does not classify hardware performance bottlenecks.
15	N/A	The PR diff is provided directly in the review prompt.
16	PASS	`dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825` factors the existing `WIDE_OK` check into `wide_kv_load_fits` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:141` reuses `_kv_block_bytes` instead of duplicating block-stride arithmetic.
17	N/A	This PR does not add or modify standalone scripts.
18	PASS	The KV-addressing refusal and 3D launch guards are proved to fire past 2 GiB on the wide loader and past the buffer range on the async loader (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:576-597`, `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:609-633`) and to pass when safe (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:568-574`…
19	PASS	The test fixture uses `_AT_2GIB = 131072` (between `0x7FFF0000` and `0x80000000` bytes) and `head_size=256` (65534 vs 65535 blocks) to distinguish wide vs async loader limits across all gates: spec builder, cache key, `_run_3d_tiled_on_stream`, `make_explicit_attention_3d_specs`, and `with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:500-655`).
20	N/A	The PR does not add or modify a text detector or linter for banned claims.
21	N/A	The PR does not add or modify any performance measurement or benchmarking harness code.
22	PASS	The added unit tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:549-655` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:317-330` run directly on CPU without skip guards or golden error entries.
23	N/A	The PR fixes a KV-cache size refusal boundary on gfx942 3D and makes no performance or speedup claims.
24	N/A	The PR does not re-bless or touch any golden IR fixtures.
25	N/A	The PR does not contain a codegen micro-optimization; emitted kernel IR is unchanged.
26	N/A	The PR is a correctness fix for KV-cache bounds and does not report benchmark comparisons.
27	N/A	The PR does not present a performance or routing A/B experiment.
28	N/A	The PR does not present counterfactual performance comparisons.
29	N/A	The PR does not swap any guarded math primitives for fast approximations.
30	N/A	The PR does not make register-spill or scratch-memory claims.
31	PASS	The PR description and mutation check verify the baseline defect on `develop` (`_enable_i64_kv_addr` rejecting 2 GiB caches on gfx942 3D in `dnn-providers/hip-kernel-provider/rocke/library/builders/common/attention_spec_builder.py:400`).
32	N/A	The PR does not report performance, VGPR, or spill measurements.
33	PASS	Resolved since previous review: the PR description now includes a 288-case differential table comparing the PR base against this branch across `arch` (gfx942/gfx950), K/V loader (wide, async, fp8 dequant), head size (64/128/256), block size (16/32), KV heads (4/8), and cache size boundaries for the pure decision functions (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909-2948`…
34	N/A	The PR does not add or modify an opt-in kernel output flag.

§H graded 5/5

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:330 and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:2909 validate `num_kv_blocks * block_bytes` at spec build, and dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4437 host-validates the launch `k` tensor shape against `_3d_spec_kv_addr_limit` in `_run_3d_tiled_on_stream` before launch.
2	N/A	This PR does not add or modify device-side table lookups or indirection value handling.
3	N/A	This PR does not add or modify device-side hot-loop `div`/`mod` operations (`wide_kv_load_fits` is a host-side modulo check).
4	N/A	This PR does not add or modify device-side masks or bounds derived from runtime sequence lengths (`kv_lens`, `cu_seqlens`).
5	PASS	dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:576, dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:609, and dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:326 provide negative tests for both spec-build (`NotImplementedError`) and 3D launch-time (`ValueError` on stale `num_kv_blocks` with oversized `k` tensor) across wide and async…

§I graded 6/6

#	Verdict	Evidence
1	N/A	This PR refines the i32 KV-cache byte limit and launch guard for the 3D tiled attention kernel and does not add or modify performance benchmarks or routing selection measurements.
2	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:129-133, dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4435-4447, and dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:609-633 keep valid caches up to 2^31 bytes on the flat/wide loader and loudly reject oversized or stale-count caches with NotImplementedError or ValueError instead of silently…
3	PASS	dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:549-655 and dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:317-331 cover the default selector path, explicit tuning-space candidates, and the 3D launch guard across wide, fp8, and async loader boundaries.
4	N/A	This PR does not add or modify performance reporting tables or benchmark columns.
5	N/A	This PR does not add or update baked tuning search snapshots.
6	N/A	This PR does not introduce or modify any DSL ops or hardware-instruction-named primitives.

§J graded 7/7

#	Verdict	Evidence
1	N/A	The diff contains no Markdown design or algorithm documents.
2	N/A	The diff contains no Markdown design or algorithm documents.
3	N/A	The diff contains no Markdown design or algorithm documents.
4	N/A	The diff contains no Markdown design or algorithm documents.
5	N/A	The diff contains no Markdown design or algorithm documents or complexity claims.
6	N/A	The diff contains no Markdown design or algorithm documents.
7	N/A	The diff adds no new Markdown documentation files.

§K graded 13/13

#	Verdict	Evidence
1	N/A	The diff does not add or modify any candidate definitions or `KnobSpace` subclasses.
2	N/A	No kernel spec fields or `KnobAxis` declarations are added, removed, or reclassified.
3	PASS	`use_i64_kv_addr` is a problem/runtime field specialized in `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082` and `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:313` without changing what any `config_key` or `tuning_id` names (verified in `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:320`).
4	N/A	The diff does not touch `KnobSpace.defaults()` or `KnobSpace.recorded()`.
5	N/A	The diff does not modify knob drop, inertness, or refusal rules in a `KnobSpace`.
6	PASS	Policy-free construction in `dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:313` computes `use_i64_kv_addr` via the pure rule `gfx942_3d_kv_needs_i64_addr` using the explicit `knobs` and `tile` rather than calling production selector heuristics `_enable_i64_kv_addr_3d` or `_enable_gfx942_3d_wide_kv_load`.
7	N/A	The diff does not touch `KnobSpace.base(req)` or request normalization.
8	N/A	The diff does not touch knob value normalization or axis type coercion.
9	N/A	The diff does not touch benchmark replay, `spec_hash` verification, or `PinRefused` handling.
10	N/A	The diff does not touch `KnobSpace.find` or bare `tuning_id` resolution.
11	N/A	The diff does not touch sweep entry points or harness loops.
12	N/A	The diff does not reorder production stacks, change `accept_default`, or alter `auto` selection.
13	N/A	The diff does not touch benchmark harnesses or claim that sweeps drive `auto` selection.

§L graded 10/10

#	Verdict	Evidence
1	N/A	The diff does not add or modify a gfx target or touch arch_specs.json / C++ arch data.
2	N/A	The diff does not add or modify any MMA op_id or fragment layout maps.
3	N/A	The diff does not touch MMA selection, MfmaAtom catalogs, or MMA lowering.
4	N/A	The diff only factors out an existing gfx942-specific wide KV load divisibility check in `dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:325` and does not touch platform wave_size…
5	N/A	The diff does not introduce cross-arch recipe sharing, transpose-LDS reads, K-packed atoms, or AsyncTileLoader changes.
6	N/A	The diff only modifies files under `library/` and does not touch `ArchTarget`, `core/arch/`, or `python/rocke/`.
7	N/A	The diff does not add or change logical dtypes, bit packing, instruction fragments, or FP8 dialect rules.
8	N/A	The diff does not touch scaled-MMA contracts or WMMA/MFMA scaled emission.
9	N/A	The diff does not add a new architecture target.
10	N/A	The diff does not touch intrinsic arch-domain artifacts or LLVM flavor membership lists.

§M graded 10/10

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:825-827 uses pure host-time integers (T, HD, THREADS, WIDE_ELEMS) via wide_kv_load_fits(T, HD) without branching on SSA Values.
2	N/A	The diff does not touch legalize_for_target or any target legalization pass.
3	N/A	The diff does not touch IR printing or ck.dsl.ir/v1 serialization.
4	N/A	The diff does not touch portable IR schemas, importers, recorders, or magic division helpers.
5	N/A	The diff does not modify AsyncTileLoader usage or LDS layout/wait emissions.
6	N/A	The diff does not emit barriers, device memory loads, selects, or cross-lane shuffles.
7	N/A	The diff does not touch buffer resource word 3 or temporal cache hints.
8	N/A	The diff does not add intrinsic declarations or modify lowering engine selection.
9	N/A	The diff does not touch C++ public entry points or headers under cpp/include/rocke/.
10	N/A	The diff does not touch debug info emission or DWARF consumers.

§N graded 18/18

#	Verdict	Evidence
1	N/A	No helpers are added or promoted to platform/python/rocke/helpers/ in this diff.
2	N/A	The diff only refactors an existing integer divisibility check into wide_kv_load_fits and does not modify MFMA mapping, TensorView addressing, loaders, epilogues, or pipelines.
3	N/A	No SoftwarePipeline usage or configuration is added or modified in this diff.
4	N/A	No fused kernels, EpilogueOp definitions, or fusion schedules are touched in this diff.
5	N/A	No public or private APIs in rocke.helpers.tiling are added or changed in this diff.
6	N/A	No front-door/toolbox tiling helpers or LayoutStyle classes are added or modified in this diff.
7	N/A	No tiling layout overrides, accumulator descriptors, or MMA issue gates are modified in this diff.
8	N/A	No tiling memory primitives (lds_tile_alloc, lds_store, lds_read, or tiling global loads) are used or modified in this diff.
9	N/A	No N-D tensor axis roles, batch reductions, or FlowStage label transforms in helpers/tiling are touched in this diff.
10	N/A	No changes are made to tiling emit, LDS staging, or MMA issue in helpers/tiling.
11	N/A	No TileMma, Tiling, lds_swizzle, or derive_sched_group_counts APIs are used or changed in this diff.
12	N/A	The PR makes no LDS bank-conflict or memory coalescing claims and does not touch tiling analysis tools.
13	N/A	No WarpDistributionEncoding, make_tile_desc, or RegisterMapper code is used or modified in this diff.
14	N/A	No tiling verbs, LDS barriers, or pipeline variants are added or modified in this diff.
15	N/A	No tiling descriptor allocation or swizzled/padded bounds checks are added or modified in this diff.
16	N/A	No layout_optimizer, recommend(), or evaluate_transform calls are touched in this diff.
17	N/A	No changes are made to tiling_recorder, roundtrip analysis, or tiling visualization.
18	N/A	No InterleavedStyle layouts, tiling demo kernels, or tiling numeric gates are touched in this diff.

§O graded 16/16

#	Verdict	Evidence
1	N/A	The diff only touches `library/` attention files and does not modify IR verification, address spaces, or required attributes in `platform/`.
2	N/A	The diff does not emit or modify `scf.for` regions, terminators, or block emission in `platform/`.
3	N/A	The diff does not touch IR emission, SSA naming, intrinsic tables, or metadata slots in `platform/`.
4	N/A	The diff does not modify IR type definitions, `SmemType`, or IR parsing in `platform/`.
5	N/A	The diff does not touch `core/passes.py`, `cpp/core/passes.cpp`, or op purity tables.
6	N/A	The diff does not touch constant folding passes in Python or C++.
7	N/A	The diff does not modify kernel attributes, codegen policy, or COMGR options in `platform/`.
8	N/A	The diff does not set or modify `CodegenPolicy` or `SchedulerStrategy`.
9	N/A	The diff does not modify waitcnt encoding or barrier lowering in `platform/`.
10	N/A	The diff does not touch LLVM lowerers or parameter attribute handling in `platform/`.
11	N/A	The diff does not touch `platform/` core internals or `ArchTarget` definitions.
12	N/A	The diff does not touch `platform/` core internals or target catalog width/size caps.
13	N/A	The diff does not touch any public C structs, enums, or ABI versions under `cpp/include/rocke/`.
14	N/A	The diff does not touch any C++ files, headers, bindings, or CMake files.
15	N/A	The diff does not touch C++ engine fallback logic, LLVM flavor resolution, or lowering backends.
16	N/A	The diff does not touch C++ library codegen or `known_gaps.md` areas in `platform/`.

§P graded 14/14

#	Verdict	Evidence
1	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/gfx942/attention_tiled_3d.py:344 keeps build_unified_attention_3d_tiled(spec, *, arch='gfx942') with use_i64_kv_addr as a defaulted field on UnifiedAttention3DTiledSpec at line 133.
2	N/A	The diff does not touch kernarg signatures, argument packing, GEMM, or convolution ABIs.
3	N/A	The diff does not touch launch grid geometry or GEMM/convolution launch sizing.
4	N/A	The diff does not touch LDS capacity gates or LDS buffer allocation.
5	N/A	The diff does not touch WMMA/RDNA GEMM, wave_size reductions, or multi-D/multi-ABD GEMM instances.
6	N/A	The diff does not touch Stream-K, MoE sorting, fused MoE, or split-K workspaces.
7	N/A	The diff does not touch Stream-K, persistent GEMM, GroupedGemmLauncher, or SUPPORT_MATRIX.md.
8	N/A	The diff does not touch quantization helpers or MX GEMM scale decoding.
9	N/A	The diff does not introduce or modify numeric emulation or floating-point decode math.
10	N/A	The diff does not touch manifest emitters, manifest schemas, or run_manifest.
11	N/A	The diff does not touch runtime kernel launchers, stream synchronization, or WorkspacePool.
12	N/A	The diff does not touch COMGR or HIP library loading.
13	PASS	dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4050 updates _tiled_3d_cache_key via _enable_i64_kv_addr_3d and line 4437 adds the _run_3d_tiled_on_stream launch guard (_3d_spec_kv_addr_limit), tested in dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:598 and line 609, and verified with gfx942 GPU numeric tests in the PR test plan.
14	N/A	The diff does not touch examples, expected.json files, platform instances, or helpers/.

§Q graded 7/7

#	Verdict	Evidence
1	N/A	This PR only adds test methods to existing `rocke/library/tests/` files and adds or removes no test files or `platform/` tests.
2	N/A	This PR does not introduce a new kernel family or variant; it adjusts the i32 KV-cache byte limit selector logic and launch guard for the existing tiled 3D kernel.
3	N/A	This PR does not modify or rely on platform differential gates alone; numerics on gfx942 and unit tests are provided for a library selector and launch-guard change whose emitted IR is unchanged.
4	N/A	No goldens are re-blessed and the valid spec space in the lowerer or builder is not widened (`use_i64_kv_addr` remains rejected by `UnifiedAttention3DTiledSpec`).
5	PASS	New tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:524-656` mock the architecture (`_patch_arch`), memo table (`_3D_KV_ADDR_LIMITS`), and pipeline build (`_get_3d_pipeline`) so they run portably on CPU without a GPU or torch.
6	N/A	This PR does not refactor any gate or test harness.
7	N/A	This PR modifies Python library spec-selection thresholds and launch guards rather than the platform C++/Python backend rejection contract.

§R graded 11/11

#	Verdict	Evidence
1	N/A	The diff introduces no new kernel body, algorithm, tiling strategy, pipeline variant, or structural performance claim, only KV-addressing capacity-limit checks.
2	N/A	The diff modifies no performance lever in the kernel builder or heuristic defaults.
3	N/A	The diff touches no GEMM, LDS, prefetch, ISA, or launch-shape optimization lever.
4	N/A	Emitted kernel IR and ISA are unchanged by this PR; no performance primitive was modified.
5	N/A	The diff adds or changes no global memory access in any kernel body (only extracts wide_kv_load_fits as a helper).
6	N/A	The diff makes no LDS or MMA layout changes.
7	N/A	The PR makes no bottleneck claim or performance optimization change.
8	N/A	The diff changes no waits, barriers, or scheduling hints.
9	N/A	The PR fixes a functional NotImplementedError regression at 2 GiB KV cache size and adds a launch-time cache-size guard, not a performance regression or shape-trading lever.
10	N/A	The diff makes no codegen, occupancy, or benchmark claims.
11	N/A	The PR is a bug fix for KV cache capacity bounds and introduces no new optimization lesson, probe, or analysis tool.

§S graded 8/8

#	Verdict	Evidence
1	N/A	The diff does not add any public symbol to the `rocke` platform package (`rocke`, `rocke.core`, `rocke.runtime`, `rocke.analysis`, `rocke.helpers`, `rocke.instances`, `rocke.dispatch`) or any `rocke_*` C entry point…
2	PASS	The behavior updates to `AttentionTuningSpec.with_num_kv_blocks` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/common.py:1082`), `make_explicit_attention_3d_specs` (`dnn-providers/hip-kernel-provider/rocke/library/dispatch/attention/tuning_specs.py:312`), and `_run_3d_tiled_on_stream` (`dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py:4437`) update existing tests in…
3	N/A	The diff does not remove or rename any public API.
4	N/A	The diff does not touch any `__all__` list or add symbols to platform package roots.
5	PASS	The tests in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:554` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:324` assert exact byte limits (`2**31` and `0x7FFF0000`), spec field values (`use_wide_kv_load`, `use_i64_kv_addr`), cache-key equality/inequality, and negative `NotImplementedError` / `ValueError` raises one block past the loader limit (including the…
6	PASS	All new and updated spec-building, cache-key, launch-guard, and tuning-spec limit checks run on CPU in `dnn-providers/hip-kernel-provider/rocke/library/tests/test_selector_parity.py:549` and `dnn-providers/hip-kernel-provider/rocke/library/tests/dispatch/attention/test_tuning_space.py:317` without requiring a GPU or torch.
7	N/A	The diff only touches the Python-only gfx942 3D attention kernel (`attention_tiled_3d.py`) and library dispatch/selector/launch helpers, which have no C++ twin or C ABI binding.
8	N/A	The diff touches only `rocke/library/` and does not modify `rocke/platform/` code, manifests, runtime, or any API used in `rocke/platform/python/rocke/README.md`.

assistant-librarian · 2026-10-26T19:32:32Z

TheRock Submodule Bump Activity

Newest first

2026-10-26 — Included in TheRock via ROCm/TheRock#9489.

The case study sends readers to the series' commits to replay its A/Bs. Those predate later fixes to the 3D kernels: the softmax-update overflow fix (#14276) and the gfx942 K/V cache bound (#14216). The two transposed QK commits wrote the update lines that #14276 rewrote, and the native exp2 commit edits them too, in both engines, so cherry-picking or rebasing them onto a tree with the fix and resolving in their favor would restore the overflow. Say that the outcomes were measured before the fixes, replay each arm in its own detached worktree, never apply the series' kernel changes onto a tree that has the fixes, and prefer spec-field comparisons on current develop. Also say that the replay commits are the series as merged. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>

JIRA ID : AICK-2712 ## Summary This is PR 7, the last of a stack of 7 that brings the rocKE C++ unified-attention engine to parity with Python (see the stack below). It sits on PR 6. These are fixes found while checking the stack as a whole. One of them changes Python dispatch: gfx942 decode on a very large KV cache now falls back to 2D instead of raising. ## Changes All paths are under `dnn-providers/hip-kernel-provider/rocke/` unless noted. - **gfx942 tiled-3D gate rejects caches past its K/V loader (Python and C++).** - The gfx942 3D kernel has no 64-bit KV-offset path, and its spec raises `NotImplementedError` when `use_i64_kv_addr` is set. The 3D gate never looked at the KV address width, so auto dispatch picked 3D and then failed on such caches. - `supports_native_unified_attention_3d_tiled` now rejects gfx942 problems for which `_enable_i64_kv_addr_3d` holds (develop's #14216), so auto dispatch falls back to 2D, which handles i64. - Caches the selected 3D loader still reads with i32 offsets (for example exactly 2 GiB on the wide loader) stay on 3D. A forced `backend="3d"` still raises, now with the gate's reason. gfx950 is unchanged. - C++ mirrors the reject. No IR change. - **Scalar 3D reduce loop bounds in Python's order.** The bound constants were unsequenced call arguments, which GCC evaluates right to left. The `.ll` is identical, but `run_diff.py --mode ir --canonical` reported STRUCT_DRIFT on `attention_unified` 16–17. They are now sequenced locals. - **Reject messages.** - The C++ gfx942 tiled-2D validator now raises Python's exact text for the fp8 K/V cache reject and the gfx950-only knob reject, which names the offending knobs. - The gfx942 and gfx950 Python `num_warps` error no longer names a product; hardware is referred to by device ID only. Message text only. - **`emit_lse` (develop's #13955).** The C problem has no LSE slot (the C engine's LSE port is deferred upstream), and the problem bindings dropped the key. So a problem asking for LSE was answered as LSE-off. Every problem binding now refuses `emit_lse=True` with `NotImplementedError`. - **CTest tier labels:** `ROCKE_ENGINE_test_categories_external.yaml` (at the hip-kernel-provider root) lists the six CTest entries the stack registers, in `quick` and `ffm-quick`. Without a tier label, `ctest -L <tier>` in provider CI skips them. - **Housekeeping:** a stale table fragment in `known_gaps.md` §7, and a stale comment in the routing test. Co-Authored-By: Claude <noreply@anthropic.com>

…orward attention on gfx942/gfx950 (#14367) ISSUE ID : AICK-2772 ## Summary Forward-attention GPU-time optimizations on gfx942 and gfx950 for both rocKE KV layouts: the unified split-KV kernels (paged KV cache, plus non-paged strided-KV decode, which runs on the same 3D kernel) and the dense kernels (contiguous, non-paged Q/K/V). Measured against the 251-shape SDPA forward suite (decode, causal prefill, chunked prefill, sliding window with sinks, FP8 KV, head_size 192). Several changes build on #14216, #12714, #14276 and #14349; all four have landed on develop and this branch merges develop, so none of them appear in the diff. The results table below was measured at `afbf60ed85c`, before the latest develop merge; a refresh against the new develop is in progress. Python and C++ engines change together; byte-identity is green at every LLVM flavor. ## Optimizations **Decode (unified split-KV)** - Split-KV for GQA ratios that do not divide the 16-row q-block (e.g. 5, 6, 12), with padding-row store masking in the 3D kernel. - Route decode to the split-KV kernel when the 2D body is occupancy-bound (gfx942 and gfx950). - Head-size-256 decode split sizing (at least two pages per segment; about two workgroups per CU on gfx942), and a decode segment cap that counts one q-block per sequence. - LLC-aware K/V cache policy: stream K/V only when the per-call K+V read exceeds the last-level cache. **Dense prefill** - gfx942: 128-row query tile when the 256-row grid under-fills the device; transposed-V path with a NaN-free RNE pack for bf16 head_size 128. - gfx950 persistent body: softmax VALU trim (folded scale FMA, pair-reduced row sums) and K/V DMA overlapped with compute through LDS alias scopes (head_size 128). - Bottom-right causal on gfx942 dense, and a KV-segment split for dense prefill on both arches with a wave-filling segment count, so chunked prefill (Sq < Skv) runs on the dense kernels. - gfx942 sliding window: narrow-window geometry, a band-phase split, and a wave-uniform skip of fully masked tiles; the 128-row under-fill rule also covers head_size 64 and sinks. - gfx950 sliding window and sinks: the single-batch 32x32 combo admits windows and sinks at head_size 64/128, and dense windows get a 128-row default tile when the 256-row grid is not already full. - gfx950 persistent wide-DMA body: 128-row tile when the 256-row work count leaves the device under-filled, and default dispatch routes under-filled plain-causal head_size 128 to it. - gfx950 head_size 256 unified prefill: query blocks run longest-first, so the costly causal tail no longer finishes last. **Coverage and dispatch** - head_size 192 in the unified tiled kernels on both arches: single-batch combo on gfx950; on gfx942, prefill on the lean 4-warp body and decode with Q staged through the V LDS slot (3 workgroups per CU instead of 2). - FP8-KV prefill on the gfx950 single-batch 32x32 combo; FP8 prefill without a 2D kernel now takes the split-KV path instead of the scalar fallback. - Dense auto-selection for contiguous-layout prefill in `dispatch_attention`; contiguous-layout decode (Sq=1) now routes to strided split-KV decode, and the strided-decode support check follows the kernel gate, so GQA ratios 5/6/12 and head_size 192 dispatch too. **Fixes found along the way** - FP8 K/V scales are now forwarded through the explicit tuning binding. - The gfx950 3D page-id K/V loader handles partial-row copies (head_size 192). - The 3D K/V LDS swizzle is rejected when the chunks per row are not a power of two. - The dense KV-segment count is capped so the fp32 workspace index stays in int32 range. - The gfx942 lean 4-warp body (head_size 256 and 192) bounds every K/V, block-table and Q read to the sequence; odd-length sequences previously read past the cache. - Sink requests on the transposed path keep scalar softmax state, so sinks land on the right rows. - `DenseSpace.defaults()` fingerprints only the knobs a shape does not record, so a tuning ID replays across chunk shapes. ## Results rocKE against itself, GPU-only, geomean speedup of the faster of the unified and dense kernel per shape (higher is better). Each cell gives geomean / median speedup and the number of shapes faster / slower by more than 2%. All arms passed the on-silicon numeric check (max |error| <= 0.05 against an fp64 reference) in the measured runs. | Arch | Config | develop -> cherry-picks (#14276, #14349) | develop -> this PR | cherry-picks -> this PR | Newly covered shapes | |---|---|---|---|---|---| | gfx950 | tuned per-shape configs | +0.1% / +0.0% (faster 8, slower 6 of 240) | **+7.0%** / +2.5% (faster 128, slower 1 of 240) | **+6.9%** / +2.7% (faster 130, slower 2 of 240) | 9 | | gfx950 | default dispatch | +0.0% / +0.0% (faster 6, slower 7 of 240) | **+34.0%** / +7.7% (faster 160, slower 1 of 240) | **+33.9%** / +7.2% (faster 165, slower 1 of 240) | 9 | | gfx942 | tuned per-shape configs | +0.5% / -0.2% (faster 5, slower 15 of 238) | **+57.5%** / +19.1% (faster 170, slower 2 of 238) | **+56.6%** / +19.7% (faster 175, slower 1 of 238) | 11 | | gfx942 | default dispatch | +0.6% / +0.0% (faster 16, slower 25 of 238) | **+57.0%** / +18.3% (faster 170, slower 6 of 238) | **+56.1%** / +18.8% (faster 169, slower 3 of 238) | 9 | By workload, cherry-picks -> this PR (gfx950 / gfx942, default dispatch unless noted): - decode: +63.3% / +148.5% (tuned configs: +0.6% / +149.4%, see caveats) - causal prefill d128/d256: +7.5% / +19.5% (tuned configs: +10.4% / +19.5%) - prefill d64: +5.1% / -0.1% (tuned configs: +4.9% / +0.9%) - chunked prefill: +50.2% / +4.4%; with the dense kernel serving Sq < Skv on gfx942, +225.6% (2.2x to 6.1x on 9 shapes, measured separately) - sliding window and sinks: +49.4% / +21.6% (tuned configs: +3.5% / +24.0%) - FP8 KV prefill: +513% on gfx950 (2 shapes); on gfx942, 2 shapes newly covered under tuned configs - head_size 192: newly covered (9 shapes per arch: 4 prefill, 5 decode) - non-paged (strided-KV) decode, measured separately on all decode shapes: +7.7% (gfx950) / +12.4% (gfx942) geomean, plus 20 shapes the cherry-pick base rejects (GQA ratios 5/6/12 and head_size 192) **Method.** Each kernel call is captured 64 times in a HIP graph; 1 warm replay and 4 timed replays, upper median per shape. Three trees: develop (`98737a5c5f4`, the develop this PR merged), cherry-picks (develop plus #14276 and #14349, `8617b561496`), and this PR (`afbf60ed85c`). Per arch and config, all three trees ran one after another in the same job, on the same node; both gfx950 jobs ran on one node and both gfx942 jobs on another, one sample per cell. On gfx942 the four FP8 shapes are excluded from the default-dispatch rows, because develop and the cherry-picks run them on the scalar fallback. Software: torch 2.13 / ROCm 10.0 wheels, LLVM 23 comgr, `ROCKE_LLVM_FLAVOR=llvm23`. "Tuned per-shape configs" pins each shape's kernel configuration from a tuning run that predates this work; "default dispatch" calls `dispatch_attention` with no pinned configuration. **Caveats.** These results hold for the measured configurations only. Because the pinned per-shape configurations predate this work, they still select the earlier decode and chunked-prefill kernels on gfx950 (decode +0.6% tuned against +63.3% default); the default-dispatch rows show those gains, and re-tuning the configurations would expose them. On gfx942, the dense path for chunked prefill is reached only when the caller routes Sq < Skv to dense; the +225.6% figure uses such a caller. ## Verification - Byte-identity gate (Python vs C++ engine LLVM IR) GREEN at llvm20, llvm22 and llvm23, all families, with new emitter configs for the GQA-ratio-5 and head_size 192 3D paths. `test_rocke_ci_static.py` 5/5. - Python vs C++ lowerer parity (`test_attention_ir_cpp_parity.py`, with the `rocke_engine` extension built): every `attention_dense` and `attention_d256` case byte-identical at all three flavors. - CPU pytest after the develop merge: `library/tests -k "attention and not bwd"` 1961 passed, 3 failed; `library/tests/dispatch` 1593 passed, 2 failed. Two of the failures were `test_unified_lse_dispatch.py` config keys that moved with the K/V cache-policy change; they are re-pinned in the last commit, and that file now passes 31/31. The remaining failure (`TestMaskScalar::test_scalar_matches_reference[mixed-no_mask]`) also fails on develop. - Off-suite GPU parity stress on both arches (non-power-of-two GQA ratios with multi-block prefill, bottom-right offsets with KV segments, sliding-window boundaries, fully masked rows, large logits, FP8, head_size 192; at least 3 seeds): 0 failures, 0 NaN/Inf; positive controls with a deliberately shifted mask fail as expected. - Known pre-existing issue, unchanged by this PR: a comgr codegen failure for gfx950 head_size 256 with block_size 64. --------- Co-authored-by: Adam Osewski <Adam.Osewski@amd.com> Co-authored-by: Claude <noreply@anthropic.com> Co-authored-by: dlangbe <David.Langbehn@amd.com> Co-authored-by: Anton Gorenko <anton@streamhpc.com>

…ime (#14530) JIRA ID : AICK-2676 The gfx942 tiled attention kernels (2D, 4-warp GQA, 3D split-KV and reduce) now read the head counts and the sliding-window size as kernargs and derive the `cu_q` search trip count from `num_seqs`. One compiled binary therefore serves every head pair at a given GQA ratio, every window size and every batch. This is the kernel-side readiness hipDNN AOT packaging needs: a packaged catalog ships one binary per kernel symbol and cannot enumerate head counts, window sizes or batch sizes. Follow-up to #13372 and #13889, which removed raw shape fields from the tiled and scalar cache keys. Builds on #14216 and #14349, merged from develop. The gfx950 counterpart (AICK-2675) reuses the plumbing added here. ## Risk Assessment Risk 4. Every gfx942 tiled kernel changes its argument list and emitted IR, the tiled cache keys change, and the paged K/V descriptor gains runtime strides in both engines. That is a performance-critical path. Mitigations: byte identity is GREEN at llvm20, llvm22 and llvm23 for every family; gfx950 and gfx1250 tiled IR is unchanged (golden); and the gfx942 numerics and an A/B against develop were run on hardware (see Testing). ## ASIC Coverage - **gfx942:** all kernel changes. Verified manually on gfx942: numeric tests, the existing gfx942 GPU suites, and a develop-vs-branch A/B. Superbuild and TheRock CI do not run these GPU numerics on gfx942. - **gfx950 / gfx1250:** host-only changes (signature helpers, cache keys, launch-cache keys). Their tiled spec classes declare no runtime kernargs, so their IR and goldens do not move. PR CI is sufficient. ## Testing Summary - **Byte identity:** full `check_byte_identity.py` GREEN at llvm20, llvm22 and llvm23. The gfx942 2D, 2D stress, 3D and reduce emit configs cover windowed, i64 and sinks specs. - **Goldens:** the representative-IR golden moves only for the gfx942 tiled cases (2D, 3D, reduce and both 4-warp kernels); the strided-KV library golden only for its gfx942 configs. Every gfx950 and gfx1250 entry is unchanged. - **Cache keys (CPU):** - shapes that differ only in head pair (same GQA ratio), window size or batch bucket share one key and lower to byte-identical IR at every flavor, on 2D, 4-warp D256, the 4-warp D128 fold and 3D; - the invariant sweep holds; - gfx950 and gfx1250 still split on the batch bucket. - **Launch signature (CPU):** every production builder route and three gfx942 tuning candidates are checked: the kernel's params equal its launch signature by name and type. - **One binary, many shapes (gfx942 GPU):** `test_attention_gfx942_runtime_shape_numeric.py` runs pairs of shapes that share a key back to back through `run_unified_attention_torch`. The second launch must compile nothing, and both outputs must match an fp32 paged reference (max_abs ≤ 4e-2; bf16/fp16 inputs, randn) with unused block-table slots on a poison block. - Pairs cover 2D default, windowed 2D, D256 4-warp, the D128 window fold, 3D decode and two-token 3D. One pair changes only the head counts at identical token counts. - Checked against mutants: baking the window back in fails the windowed pair (max_abs 0.88); baking the kv head count into the K/V stride faults on the device. - **Existing GPU suites (gfx942):** 69 attention, MLA and strided-KV library test files. Results match develop; the remaining failures fail identically on develop (MLA comgr environment errors, strided-KV and selector-parity cases). **A/B, develop vs this branch (gfx942, 304 CUs)** - **Workload:** 116 problems through `run_unified_attention_torch` with production routing (`backend="auto"`): 98 on the 2D path, 18 on 3D. Cohorts cover d64/d128/d256, bf16/fp16 and fp8 K/V, GQA ratios 1, 4 and 8, sinks, sliding window, the 4-warp D256 and fold paths, and a 64/16 head pair. - **Method:** HIP-event mean over 50 launches after 10 warmup, median over 3 rounds. Arm order alternates per round, and each arm runs in a fresh process each round. - **Toolchain:** torch 2.13.0+rocm10.0.0, LLVM 23 from the ROCm 10 SDK wheels, Python lowering. - **Baseline:** develop at `f37a7056c791`. - **Numeric gate:** every row of both arms is within 4e-2 of an fp32 reference; worst max_abs is 1.24e-2 in both arms. - **Results (branch / develop):** | Measure | Result | |---|---| | Compiled binaries per process | 18 vs 54 | | Total first-launch time | 0.37× | | Steady state, geometric mean over 116 problems | 0.994× (range 0.87–1.06×) | | Per cohort | within 0.98–1.01×, except the two below | | d64 GQA-8 block-32 **sinks** (2 problems, 2D) | 1.05–1.06× | | d64 GQA-8 **fp8 K/V** decode (4 problems, 3D) | 1.01–1.03× | - **Sinks caveat, isolated:** - Timing each commit puts the whole sinks cost in the head-count commit, and only on the narrow 2D kernel. - A timing-only variant with the K/V token stride restored to a constant removes it; restoring the query head count changes nothing. - The per-copy K/V offset now multiplies the token index by the runtime stride inside the KV loop, where the constant stride used to compile to a shift. - Accepted here as a known cost. Hoisting the in-page offsets out of the loop belongs with the planned per-page i32 K/V loader rework. **AOT dry run:** a draft engine manifest pinned to one gfx942 tuning candidate (`transposed_x8`, 4 warps, tile 4× block) expands with `registry_enumerator.py --plan-space`: 24 cells (6 head configurations × bf16/fp16 × block 16/32), production sweep, 20 varying knobs. Result: - 324 instances (within the default per-arch budget of 1000); - 162 distinct kernels on this branch against 324 on develop, because head pairs at one GQA ratio now build the same kernel. ## Testing Checklist - [x] Byte identity - `ROCKE_LLVM_FLAVOR=llvm{20,22,23} python tools/check_byte_identity.py` - Status: Passed - [x] Representative-IR golden - `python tests/instances/rocke_ir_parity_harness.py --check tests/golden/rocke_representative_ir_sha256.json` - Status: Passed - [x] Library host tests (attention, MLA, strided KV, dispatch, layering), GPU hidden - `python -m pytest <file>` per file - Status: Passed (3 files fail identically on develop) - [x] Platform dynamic-descriptor tests - `python -m pytest tests/core/test_transforms_dynamic.py` - Status: Passed - [x] gfx942 GPU: new runtime-shape numeric test - `python -m pytest tests/test_attention_gfx942_runtime_shape_numeric.py` - Status: Passed (14/14) - [x] gfx942 GPU: existing attention/MLA/strided-KV library suites (69 files) - Status: Passed, matching develop - [x] gfx942 GPU: develop-vs-branch A/B, 116 problems, 3 rounds - Status: Passed (numeric gate), caveats above ## Technical Changes - **Runtime-kernarg plumbing.** Tiled spec classes declare `RUNTIME_KERNARG_FIELDS`. `_tiled_2d_signature` / `_tiled_3d_signatures` append those fields to the launch signature, and `_runtime_kernarg_values` packs them. Every gfx942 launch site uses the arch-aware signature. The 4-warp GQA kernels now declare `qq_bias_stride_0`, which the shared 2D signature already passed. - **Search trip count.** `binary_search_seq_idx_trip_count` computes `bit_length(num_seqs)` from the `num_seqs` kernarg. It's exact below 2^24 sequences; past that it adds at most one no-op iteration. Specs declare `RUNTIME_SEARCH_ITERS` and the keys drop the batch bucket. The existing helper and its other callers emit the same IR. - **Sliding window.** The size is a kernarg. Whether a window applies still selects structure, so the name token is `sw` and the keys carry `window > 0`. - **Head counts.** `num_query_heads` and `num_kv_heads` are kernargs. The Q/O, segment-output and paged K/V strides are runtime values through `DynamicTensorDescriptor`, which now takes mixed int/Value strides plus runtime strides in `offset_i64_split` (both engines) and `offset_i64` (Python). Names carry `g<Hq/Hkv>`, and the keys carry the GQA ratio. Every selector that reads absolute head counts feeds an output that's already keyed. - **Launch caches.** `_shape_key` (2D grid, 3D grids and workspace) now carries both head counts, since one binary now serves several head pairs. - **i64 name token.** The gfx942 2D name carries `i64` when `use_i64_kv_addr` is set; i32 and i64 builds used to share a symbol. - **C++ twins.** The 2D, 3D and reduce twins mirror all of the above. The gfx942 2D C++ entry also builds the gfx950 fastKV register-P twin, so its runtime changes are gated to gfx942. - **CI enrollment.** `test_attention_tiled_launch_signature.py` joins the installed attention CPU cohort; `test_attention_gfx942_runtime_shape_numeric.py` joins the library GPU cohort. **ABI note:** in this repo, the gfx942 tiled kernels are launched only through `run_unified_attention_torch`, the dispatch tuning candidates and the harnesses updated here. Anything that launches them by name must append `num_query_heads`, `num_kv_heads` and `sliding_window` (2D and 3D) or `num_query_heads` (reduce). **Notes for the packaging work:** - The gfx942 fast paged-KV descriptor path (`use_fast_paged_kv_desc`, reachable only through the `fastkv` tuning knob) still hard-codes 64/8 heads, pinned by its spec validator. A packaged catalog must serve it only at 64/8 or leave that knob out. - gfx942 routes windowed decode to 2D, so production never takes the windowed 3D path; byte identity covers it. - `AttentionTuningSpec.cache_key()` remains field-complete, so it still splits on the runtime fields. That over-keys but is never wrong. ## Submission Checklist - [ ] Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests. --------- Co-authored-by: Claude <noreply@anthropic.com>

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Comment thread dnn-providers/hip-kernel-provider/rocke/library/kernels/common/attention_unified.py Resolved

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dlangbe changed the title ~~fix(rocke/attention): bound gfx942 3D KV cache by its K/V loader~~ fix(rocke): bound gfx942 3D KV cache by its K/V loader Oct 23, 2026

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perf(rocke/attention): GPU-time optimizations for unified and dense forward attention on gfx942/gfx950 #14367

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feat(rocke): decouple KV pages from tiled decode compute tiles #13128

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fix(hip-kernel-provider): rocKE unified-attention C++ parity follow-ups #14528

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perf(rocke): make gfx942 tiled attention heads, window and batch runtime #14530

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fix(rocke): bound gfx942 3D KV cache by its K/V loader - #14216

fix(rocke): bound gfx942 3D KV cache by its K/V loader#14216
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rocKE checklist re-review of the fixes since `c9c73c2a8e85`

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