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test(rocke): give register-bound GDN tiles a spill budget - #13351

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AviralGoelAMD merged 1 commit into
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users/avirgoel/rocke/gdn-spill-budget-test
Oct 10, 2026
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AviralGoelAMD merged 1 commit into
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users/avirgoel/rocke/gdn-spill-budget-test

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@AviralGoelAMD AviralGoelAMD commented Oct 8, 2026 •

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JIRA ID : TESTAUTO-6039

What was wrong

library/tests/test_gdn_decode_spec.py::TestEmission::test_registered_gdn_tiles_compile fails in the rocKE CPU library lane on current develop:

test_registered_gdn_tiles_compile[nw1_wtk1_bpv2]   388 != 0
test_registered_gdn_tiles_compile[nw2_wtk1_bpv1]   404 != 0

The test compiles every registered gfx950 GDN decode tile and requires 0 B scratch (no register spill), with one exemption (nw1_wtk1_bpv1). With the ROCm 7.13 comgr, two more warp_threads_k=1 tiles reach the 512-VGPR limit and spill. The rocKE IR is identical; only the compiler changed.

What changed

Area / files Crux of change
library/tests/test_gdn_decode_spec.py The three register-bound tiles are named and may spill up to 512 B. Every other registered tile must still have 0 B scratch. Every allowlisted ID must still be registered.
  • Test-only change. No kernel, dispatcher or registration change.

Why it works

  • A warp_threads_k=1 tile gives each lane the whole K=128 reduction, so it sits at the VGPR limit, and whether it spills depends on the register allocator. GDN auto never selects these tiles (it always picks DEFAULT_TILE (2,16,8): 60-65 VGPRs, 0 B on both compilers). They stay registered because they can be pinned and (1,1,1) is the fallback when DEFAULT_TILE is illegal.
  • A named allowlist with a byte budget absorbs compiler drift and still fails when a new tile spills or a known one blows up. Rejected alternatives: exempting the whole wtk1 class (an unbounded hole for future tiles) and expectations keyed by compiler version (comgr's version API reports 3.0 for both 7.1 and 7.13, and byte counts differ between 7.13 nightlies).

Measured scratch (gfx950):

Tile ROCm 7.1 ROCm 7.13
nw1_wtk1_bpv1 448 B 364 B
nw1_wtk1_bpv2 0 B (436 VGPRs) 372-388 B (512 VGPRs)
nw2_wtk1_bpv1 0 B (422 VGPRs) 376-404 B (512 VGPRs)

How we validated

Gate Result
Reproduction On develop faea76a5cde, the ROCm 7.13 comgr (ROCKE_LLVM_FLAVOR=llvm23) reproduces both failures (372 / 376 B with a July 7.13 build; CI's nightly reports 388 / 404 B). ROCm 7.1 comgr: passes.
This change test_gdn_decode_spec.py: 33 passed, 57 subtests passed with both the ROCm 7.1 and 7.13 comgr.
The test still catches spills Throwaway mutations: budget 300 B → fails on all 3 tiles; nw2_wtk1_bpv1 removed from the allowlist → fails 376 != 0.

CPU-only (comgr compile + llvm-objdump/llvm-readelf introspection; Python lowerer). ruff was not run locally.

test_registered_gdn_tiles_compile requires 0 B scratch for every
registered gfx950 GDN tile except nw1_wtk1_bpv1. With ROCm 7.13 comgr two
more warp_threads_k=1 tiles reach 512 VGPRs and spill (nw1_wtk1_bpv2
372-388 B, nw2_wtk1_bpv1 376-404 B; both 0 B with ROCm 7.1), failing the
CPU library lane. Same rocKE IR; only the compiler changed.

These tiles give each lane the whole K reduction, so they sit at the
VGPR limit. GDN auto never selects them (it always picks DEFAULT_TILE).
Name the three register-bound tiles and allow them up to 512 B, which
absorbs compiler drift but still fails on a register-pressure blowup.
Every other registered tile must still compile with 0 B scratch, and
every allowlisted ID must still be registered.
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@AviralGoelAMD
AviralGoelAMD merged commit 4bed987 into develop Oct 10, 2026
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@AviralGoelAMD
AviralGoelAMD deleted the users/avirgoel/rocke/gdn-spill-budget-test branch October 10, 2026 02:53
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