feat(rocBLAS): default to hipBLASLt for ZGEMM/CGEMM/SGEMM/fp16/bf16 on MI300A (gfx942, 228 CU) by NaveenElumalaiAMD · Pull Request #13045 · ROCm/rocm-libraries

NaveenElumalaiAMD · 2026-10-03T23:50:58Z

JIRA ID : https://amd-hub.atlassian.net/browse/AIHPBLAS-3404
JIRA ID : https://amd-hub.atlassian.net/browse/AIHPBLAS-3402
JIRA ID : https://amd-hub.atlassian.net/browse/AIROCBLAS-1334
JIRA ID : https://amd-hub.atlassian.net/browse/AIHPBLAS-3403
JIRA ID : https://amd-hub.atlassian.net/browse/AIHPBLAS-3400

Motivation

Follow-up to #12724, which defaulted DGEMM to hipBLASLt on the 228-CU MI300A. This extends the same gate to ZGEMM, fp16 and bf16 so they also default to hipBLASLt on MI300A, while MI300X and every other gfx942
variant stay on Tensile for all types.

Technical Details

useHipBLASLt() (tensile_host.cpp) previously let only double through the arch == 942 branch; the predicate is widened to sizeof(Ti) == 2 || double || rocblas_double_complex, covering fp16, bf16, DGEMM and ZGEMM. The multiProcessorCount != 228 guard is unchanged, so MI300X is unaffected, and isDefaultHipBLASLtArch() already lists 942.
Also plumbs the handle's math mode into the hipBLASLt backend (HIPBLAS_COMPUTE_32F_FAST_TF32), mirroring the Tensile path's setF32XdlMathOp(XFloat32). Without it, flipping SGEMM to hipBLASLt would silently ignore rocblas_set_math_mode(xf32) — which is what gemm_ex_get_solutions_alpha_beta caught.

Test Plan

ROCBLAS_USE_HIPBLASLT=1 ./rocblas-test --gtest_filter='blas3_tensilef64_c*-known_bug:graph_test'
ROCBLAS_USE_HIPBLASLT=1 ./rocblas-test --gtest_filter='blas3_tensilef16_r*-known_bug:graph_test'

Test Result

ZGEMM — logic validation, gtest and batch coverage all clean:

Check	Result
`run_tensile_logic_check.py` over the nine new files	7030 / 7030 solutions kept, 0 rejected
`rocblas-test` ZGEMM	30296 / 30296 PASS
Batch coverage scan (9 tables)	8696 rows, 4220 cells, B ∈ {1}, 0 cells without a B == 1 row

ROCBLAS_USE_HIPBLASLT=1 ./rocblas-test --gtest_filter='blas3_tensilef32_c*-known_bug:graph_test'
30,326 ran / 30,326 passed / 0 failed, identical in both arms.

fp16 — gtest clean, and at or above Tensile parity in all configs:

Total	Passed	Skipped
490,300	488,903	1,397

Config	tn (GFLOPS)	hb (GFLOPS)	Ratio
1 GPU, N=145920	2.329e5	3.151e5	1.35×
2 GPU, N=204800	3.455e5	3.596e5	1.04×
4 GPU, N=291840	6.508e5	6.667e5	1.02×

therock-pr-bot · 2026-10-03T23:54:39Z

✅ All Checks Passed — Ready for Review

Check	Status	Details
📝 PR Description	✅ Pass	—
⛔ Forbidden Files	✅ Pass	—
🧪 Unit Test	⚠️ Warning	Error: Source/code files changed without an accompanying unit test. Expected: add at least one test file named like `test_<name>.py` / `test_<name>.cpp` (or `<name>_test.`). Current:* code file(s) changed: `projects/rocblas/library/src/hipblaslt_host.cpp`, `projects/rocblas/library/src/tensile_host.cpp`; no test file found
🔎 pre-commit	✅ Pass	—
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therock-pr-bot · 2026-10-03T23:54:41Z

🎉 All checks passed! This PR is ready for review.

TorreZuk

You can ignore code coverage as known issue to be fixed separately.
f16/bf16 fail you could back out and investigate separately as well.

NaveenElumalaiAMD · 2026-10-05T16:52:09Z

You can ignore code coverage as known issue to be fixed separately. f16/bf16 fail you could back out and investigate separately as well.

This PR:#12609 has the fix, waiting for review on this PR to merge and then this issue should be resolved.

TorreZuk · 2026-10-08T18:33:45Z

This overlaps #13292 right?

TorreZuk · 2026-10-09T16:19:41Z

I guess fix was merged to hipblaslt but develop artifacts with fix likely needed, maybe this afternoon can rebase ?

NaveenElumalaiAMD · 2026-10-09T17:54:08Z

I guess fix was merged to hipblaslt but develop artifacts with fix likely needed, maybe this afternoon can rebase ?

this PR:#13292 now enables fp16 and bf16 for MI300A as well and once this goes in i will rebase this PR and flip sgemm and zgemm on MI300A in this PR. Thanks @shbae for the changes.

codecov · 2026-10-10T16:23:07Z

Codecov Report

✅ All modified and coverable lines are covered by tests.

Additional details and impacted files

@@           Coverage Diff            @@
##           develop   #13045   +/-   ##
========================================
  Coverage    76.04%   76.04%           
========================================
  Files         2867     2867           
  Lines       474973   474973           
  Branches     71126    71126           
========================================
  Hits        361148   361148           
  Misses       89279    89279           
  Partials     24546    24546

Flag	Coverage Δ	*Carryforward flag
TensileLite-CPP	`49.70% <ø> (ø)`	Carriedforward from bb10a9e
TensileLite-Unit	`83.55% <ø> (ø)`	Carriedforward from bb10a9e
hipBLAS	`90.62% <ø> (ø)`	Carriedforward from bb10a9e
hipBLASLt	`66.03% <ø> (ø)`	Carriedforward from bb10a9e
hipCUB	`82.68% <ø> (ø)`	Carriedforward from bb10a9e
hipDNN	`86.99% <ø> (ø)`	Carriedforward from bb10a9e
hipFFT	`42.00% <ø> (ø)`	Carriedforward from bb10a9e
hipRAND	`76.12% <ø> (ø)`	Carriedforward from bb10a9e
hipSOLVER	`69.67% <ø> (ø)`	Carriedforward from bb10a9e
hipSPARSE	`86.99% <ø> (ø)`	Carriedforward from bb10a9e
rocBLAS	`68.73% <ø> (ø)`
rocFFT	`48.10% <ø> (ø)`	Carriedforward from bb10a9e
rocRAND	`57.30% <ø> (ø)`	Carriedforward from bb10a9e
rocSOLVER	`76.74% <ø> (ø)`	Carriedforward from bb10a9e
rocSPARSE	`76.92% <ø> (ø)`	Carriedforward from bb10a9e
rocThrust	`93.15% <ø> (ø)`	Carriedforward from bb10a9e

*This pull request uses carry forward flags. Click here to find out more.

Files with missing lines	Coverage Δ
projects/rocblas/library/src/tensile_host.cpp	`0.00% <ø> (ø)`

🚀 New features to boost your workflow:

❄️ Test Analytics: Detect flaky tests, report on failures, and find test suite problems.
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…fx942 (#13292) JIRA ID: https://amd-hub.atlassian.net/browse/AIROCBLAS-1268 JIRA ID: https://amd-hub.atlassian.net/browse/AIROCBLAS-1267 JIRA ID: https://amd-hub.atlassian.net/browse/AIHPBLAS-3019 ## Motivation rocBLAS currently defaults to the Tensile Solution Library for FP16, BF16, and FP64 GEMM on gfx942. As part of the GEMM backend unification initiative, the default backend is flipped to hipBLASLt for these three input types, following the performance parity threshold of within 5% of Tensile or acceptable performance. This extends the two preceding flips — DGEMM on gfx950 (#12424) and DGEMM on the 228-CU MI300A (#12724) — as follows: * FP64 now defaults to hipBLASLt on every gfx942 device (MI300X and MI300A alike), rather than MI300A (228 CUs) only. * FP16 and BF16 now default to hipBLASLt on the 304-CU MI300X only. MI300A (228 CUs) continues to default to Tensile for FP16/BF16 in this PR, but it will be changed by #13045. * ## Technical Details `useHipBLASLt()` (`library/src/tensile_host.cpp`) previously routed only `double` to hipBLASLt on gfx942, and only when `multiProcessorCount == 228` (MI300A). The gfx942 branch for MI300x now applies FP16, BF16, and FP64. No change is needed in `isDefaultHipBLASLtArch()` (`handle.hpp`): `942` was already added there by #12724, and that function only gates eager hipBLASLt handle construction, not per-datatype routing. `docs/conceptual/rocblas-design-notes.rst` is also updated. It previously stated that hipBLASLt is the default "for problems on the gfx12 architecture", which was already stale after #12424 and #12724 flipped FP64 on gfx950 and MI300A. It now carries a table of which architectures default to hipBLASLt and for which data types. ## Test Plan 1. Confirm backend routing per datatype on gfx942 with `ROCBLAS_LAYER=8`. 2. Run the GEMM gtest suite on MI300X for regressions. ## Test Result ### Backend routing (MI300X, gfx942, `ROCBLAS_LAYER=8`) | Input type | Backend selected | |---|---| | `f16_r` | `rocblas_gemm_hipblaslt_backend` | | `bf16_r` (via `gemm_ex`, compute `f32_r`) | `rocblas_gemm_hipblaslt_backend` | | `f64_r` | `rocblas_gemm_hipblaslt_backend` | | `f32_r` | `rocblas_gemm_tensile_backend` (unchanged) | ### gtest `rocblas-test --gtest_filter='*hipblaslt*:*non_hipblaslt*-*known_bug*'`: | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 2,208 | 0 | 0 | 2,208 | 0 | `./rocblas-test --gtest_filter=*gemm*f64_r*-*known_bug*`: | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 163,672 | 0 | 44 | 163,716 | 0 | ` ./rocblas-test --gtest_filter=*gemm*f16_r*:*gemm*bf16_r*-*known_bug*` | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 497,739 | 19 | 192 | 497,950 | 0 | Those failed tests are all stress_gemm with ILP tests, which requires appropriate ILP library link, so after I rebuilt the library, I reran those failed tests as below, and all the tests PASSED. `./rocblas-test --gtest_filter=_/gemm.*stress*ILP64*f16_r*:_/gemm_ex.*stress*ILP64*f16_r*:_/gemm_ex.*stress*ILP64*bf16_r*` | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 23 | 0 | 0 | 23 | 0 | ## Submission Checklist - [ ] Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests.

… ZGEMM/SGEMM/CGEMM on MI300A

TorreZuk

If all tests passing LGTM

…fx942 (ROCm#13292) JIRA ID: https://amd-hub.atlassian.net/browse/AIROCBLAS-1268 JIRA ID: https://amd-hub.atlassian.net/browse/AIROCBLAS-1267 JIRA ID: https://amd-hub.atlassian.net/browse/AIHPBLAS-3019 ## Motivation rocBLAS currently defaults to the Tensile Solution Library for FP16, BF16, and FP64 GEMM on gfx942. As part of the GEMM backend unification initiative, the default backend is flipped to hipBLASLt for these three input types, following the performance parity threshold of within 5% of Tensile or acceptable performance. This extends the two preceding flips — DGEMM on gfx950 (ROCm#12424) and DGEMM on the 228-CU MI300A (ROCm#12724) — as follows: * FP64 now defaults to hipBLASLt on every gfx942 device (MI300X and MI300A alike), rather than MI300A (228 CUs) only. * FP16 and BF16 now default to hipBLASLt on the 304-CU MI300X only. MI300A (228 CUs) continues to default to Tensile for FP16/BF16 in this PR, but it will be changed by ROCm#13045. * ## Technical Details `useHipBLASLt()` (`library/src/tensile_host.cpp`) previously routed only `double` to hipBLASLt on gfx942, and only when `multiProcessorCount == 228` (MI300A). The gfx942 branch for MI300x now applies FP16, BF16, and FP64. No change is needed in `isDefaultHipBLASLtArch()` (`handle.hpp`): `942` was already added there by ROCm#12724, and that function only gates eager hipBLASLt handle construction, not per-datatype routing. `docs/conceptual/rocblas-design-notes.rst` is also updated. It previously stated that hipBLASLt is the default "for problems on the gfx12 architecture", which was already stale after ROCm#12424 and ROCm#12724 flipped FP64 on gfx950 and MI300A. It now carries a table of which architectures default to hipBLASLt and for which data types. ## Test Plan 1. Confirm backend routing per datatype on gfx942 with `ROCBLAS_LAYER=8`. 2. Run the GEMM gtest suite on MI300X for regressions. ## Test Result ### Backend routing (MI300X, gfx942, `ROCBLAS_LAYER=8`) | Input type | Backend selected | |---|---| | `f16_r` | `rocblas_gemm_hipblaslt_backend` | | `bf16_r` (via `gemm_ex`, compute `f32_r`) | `rocblas_gemm_hipblaslt_backend` | | `f64_r` | `rocblas_gemm_hipblaslt_backend` | | `f32_r` | `rocblas_gemm_tensile_backend` (unchanged) | ### gtest `rocblas-test --gtest_filter='*hipblaslt*:*non_hipblaslt*-*known_bug*'`: | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 2,208 | 0 | 0 | 2,208 | 0 | `./rocblas-test --gtest_filter=*gemm*f64_r*-*known_bug*`: | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 163,672 | 0 | 44 | 163,716 | 0 | ` ./rocblas-test --gtest_filter=*gemm*f16_r*:*gemm*bf16_r*-*known_bug*` | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 497,739 | 19 | 192 | 497,950 | 0 | Those failed tests are all stress_gemm with ILP tests, which requires appropriate ILP library link, so after I rebuilt the library, I reran those failed tests as below, and all the tests PASSED. `./rocblas-test --gtest_filter=_/gemm.*stress*ILP64*f16_r*:_/gemm_ex.*stress*ILP64*f16_r*:_/gemm_ex.*stress*ILP64*bf16_r*` | PASS | FAIL | SKIP | total | TEST_EXIT | |---|---|---|---|---| | 23 | 0 | 0 | 23 | 0 | ## Submission Checklist - [ ] Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests.

TorreZuk · 2026-10-14T21:30:45Z

@evedovelli it looks like get_solutions only, are all the launches guarded by can_solve checks now?

NaveenElumalaiAMD · 2026-10-14T21:47:41Z

@evedovelli it looks like get_solutions only, are all the launches guarded by can_solve checks now?

do we need to run the TF32 get_solutions test for MI300A? @TorreZuk @evedovelli?

…ip_backend

evedovelli · 2026-10-16T12:36:49Z

@evedovelli it looks like get_solutions only, are all the launches guarded by can_solve checks now?

For gemm_ex, we are iterating through all the solutions and trying to solve them. Some of them are not solvable (e.g. only works with alpha 1 but our problem requires another value for alpha) so we just ignore them, but for the ones that provide a result, we do validate those against the golden result.

…BLASLt defaults and the xf32 math mode fix

…ip_backend

… 228-CU MI300A and the 304-CU MI300X

assistant-librarian · 2026-10-19T06:37:46Z

TheRock Submodule Bump Activity

Newest first

2026-10-19 — Included in TheRock via ROCm/TheRock#9348.

…x950 (#13901) ## Motivation This PR extends hipBLASLt backend support for F32 (SGEMM) operations on both gfx942 and gfx950 architectures. Previously: - **gfx950**: F32 was explicitly disabled and defaulted to Tensile - **gfx942**: F32 was only enabled on the 228-CU MI300A configuration This change enables F32 GEMM to leverage the hipBLASLt backend for improved performance on: - All gfx950 devices (MI350 series) - Both MI300A (228 CU) and MI300X (304 CU) gfx942 devices This follows the pattern established in #13045, which defaulted various data types to hipBLASLt on specific architectures. ## Technical Details ### Changes to `tensile_host.cpp` The `useHipBLASLt()` function has been modified: 1. **gfx950 architecture (lines 1295-1301)**: - **Before**: Early return `false` for F32 types, forcing Tensile backend - **After**: All types including F32 now use hipBLASLt via `prob.handle->tryHipBLASLt()` - Removed the TODO comment about SGEMM support 2. **gfx942 architecture (lines 1303-1333)**: - **Before**: F32 was in the `only_MI300A` category, restricting it to 228 CU devices only - **After**: F32 moved to the `MI300A_or_MI300X` category alongside fp16, bf16, and fp64 - This enables F32 on both 228 CU (MI300A) and 304 CU (MI300X) configurations - Complex types (complex-fp64, complex-fp32) remain in the `only_MI300A` category ### Changes to `CHANGELOG.md` Updated the rocBLAS 5.8.0 changelog to reflect the new defaults: - **gfx950**: Updated from "every input type except real `f32_r`" to "all input types" - **gfx942**: Added `f32_r` to the list of types enabled on both MI300A and MI300X ### Key Implementation Details ```cpp // gfx950: Now enables hipBLASLt for all types including F32 if(arch == 950) { return prob.handle->tryHipBLASLt(); } // gfx942: F32 now included in MI300A_or_MI300X category constexpr bool MI300A_or_MI300X = sizeof(Ti) == 2 || std::is_same<Ti, double>::value || std::is_same<Ti, float>::value; ``` ## Impact ### Architectures Affected - **gfx950 (MI350 series)**: All devices now use hipBLASLt for F32 - **gfx942 (MI300 series)**: - MI300A (228 CU): Already supported, no change - MI300X (304 CU): Now enabled for F32 (previously Tensile only) ### Backward Compatibility - The `ROCBLAS_USE_HIPBLASLT` environment variable continues to force or disable the hipBLASLt backend, providing an override mechanism Co-authored-by: Madhusoodhanan Prabha <amadhuso@ctr2-alola-ctrl-01.amd.com> Co-authored-by: Claude Sonnet 4 <noreply@anthropic.com>

NaveenElumalaiAMD requested a review from a team as a code owner October 3, 2026 23:50

NaveenElumalaiAMD added the ci:extended label Oct 3, 2026

github-actions Bot added the project: rocblas label Oct 3, 2026

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shbae mentioned this pull request Oct 8, 2026

feat(rocblas): default to hipBLASLt for GEMM with fp16/bf16/fp64 on gfx942 #13292

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NaveenElumalaiAMD force-pushed the users/nelumala/rocblas/zgemm_fp16_bf16_flip_backend branch from a472b4e to 475e6cf Compare October 11, 2026 00:36

NaveenElumalaiAMD changed the title ~~feat(rocBLAS): default to hipBLASLt for ZGEMM/fp16/bf16 on MI300A (gfx942, 228 CU)~~ feat(rocBLAS): default to hipBLASLt for ZGEMM/CGEMM/SGEMM/fp16/bf16 on MI300A (gfx942, 228 CU) Oct 11, 2026

NaveenElumalaiAMD and others added 3 commits October 14, 2026 16:12

feat(rocBLAS): default to hipBLASLt for fp16/bf16/DGEMM on gfx942 and…

80ca019

… ZGEMM/SGEMM/CGEMM on MI300A

fix(rocBLAS): honour xf32 math mode on the hipBLASLt backend

6c869a7

doc(rocBLAS): record the MI300A hipBLASLt default data types

84bb7e1

NaveenElumalaiAMD force-pushed the users/nelumala/rocblas/zgemm_fp16_bf16_flip_backend branch from 81bf64b to 84bb7e1 Compare October 14, 2026 16:22

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Comment thread projects/rocblas/library/src/tensile_host.cpp Resolved

TorreZuk requested a review from evedovelli October 14, 2026 21:28

TorreZuk mentioned this pull request Oct 15, 2026

[develop] rocBLAS gemm_ex f16 crashes in hipBLASLt heuristic on MI300A (gfx942a) in math-ci #13413

Closed

Merge branch 'develop' into users/nelumala/rocblas/zgemm_fp16_bf16_fl…

5e058c0

…ip_backend

Fix hipblaslt_host.cpp formatting and update CHANGELOG for gfx942 hip…

deff505

…BLASLt defaults and the xf32 math mode fix

newling force-pushed the users/nelumala/rocblas/zgemm_fp16_bf16_flip_backend branch from deff505 to 5b817e2 Compare October 16, 2026 17:20

NaveenElumalaiAMD commented Oct 16, 2026

View reviewed changes

Comment thread projects/rocblas/library/src/tensile_host.cpp Resolved

newling force-pushed the users/nelumala/rocblas/zgemm_fp16_bf16_flip_backend branch from 5b817e2 to deff505 Compare October 16, 2026 21:12

NaveenElumalaiAMD and others added 2 commits October 16, 2026 15:16

Merge branch 'develop' into users/nelumala/rocblas/zgemm_fp16_bf16_fl…

b3174d3

…ip_backend

Restrict the gfx942 hipBLASLt default for fp16, bf16, and fp64 to the…

dce9a79

… 228-CU MI300A and the 304-CU MI300X

NaveenElumalaiAMD merged commit 6bb613a into develop Oct 17, 2026
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NaveenElumalaiAMD deleted the users/nelumala/rocblas/zgemm_fp16_bf16_flip_backend branch October 17, 2026 22:57

mpanoop mentioned this pull request Oct 18, 2026

feat(rocBLAS): enable hipBLASLt backend for F32 GEMM on gfx942 and gfx950 #13901

Merged

pmoutsias-amd mentioned this pull request Nov 3, 2026

Move rocBLAS changelog entries for code merged after the ROCm 10.2.0 branch to the rocBLAS 5.9.0 section #14986

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