[alex391a]

JIRA ID : AIHPSPAR-274

Motivation

Add gfx1250 support for Gate residual cache hints and correct Gate address updates for compact loop store (CLS).

Technical Details

• Add gfx1250 packed FMA mappings in stinkytofu.
• Add TemporalHintGate and NonVolatileGate.
• Fix Gate row-pointer and SRD updates for CLS.
• Add FP8 and FP16 sparse GEMM test configurations.

Test Plan

Add Tensile/Tests/common/sparse/gfx1250/spmm_gate.yaml covering FP8 and FP16 Gate residual cases.

Test Result

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests.

[therock-pr-bot]

✅ All Checks Passed — Ready for Review

Check	Status	Details
📝 PR Description	✅ Pass	—
⛔ Forbidden Files	✅ Pass	—
🧪 Unit Test	✅ Pass	—
🔎 pre-commit	✅ Pass	—
🚫 Draft PR	🔜 To Be Enabled	—
🚩 Feature Flag	🔜 To Be Enabled	—
📊 Code Coverage	🔜 To Be Enabled	—
🤖 therock-pr-bot	✅ Pass	—

🎉 All checks passed! This PR is ready for review.

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[therock-pr-bot]

🎉 All checks passed! This PR is ready for review.

[codecov]

Codecov Report

❌ Patch coverage is 20.00000% with 8 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
...blaslt/tensilelite/Tensile/KernelWriterAssembly.py	0.00%	5 Missing and 1 partial ⚠️
...tensilelite/Tensile/Components/GlobalWriteBatch.py	0.00%	2 Missing ⚠️

Additional details and impacted files

@@             Coverage Diff             @@
##           develop   #11887      +/-   ##
===========================================
- Coverage    70.23%   70.22%   -0.01%     
===========================================
  Files         2810     2810              
  Lines       462535   462588      +53     
  Branches     68103    68118      +15     
===========================================
+ Hits        324833   324840       +7     
- Misses      114182   114230      +48     
+ Partials     23520    23518       -2     

Flag	Coverage Δ		*Carryforward flag
TensileLite-CPP	46.40% <ø> (ø)
TensileLite-Unit	76.07% <20.00%> (-0.01%)	⬇️
hipBLAS	90.62% <ø> (ø)		Carriedforward from 62d6012
hipBLASLt	35.20% <ø> (-0.04%)	⬇️
hipCUB	82.68% <ø> (ø)		Carriedforward from 62d6012
hipDNN	87.02% <ø> (ø)		Carriedforward from 62d6012
hipFFT	43.07% <ø> (ø)		Carriedforward from 62d6012
hipRAND	76.12% <ø> (ø)		Carriedforward from 62d6012
hipSOLVER	68.92% <ø> (ø)		Carriedforward from 62d6012
hipSPARSE	86.99% <ø> (ø)		Carriedforward from 62d6012
rocBLAS	48.31% <ø> (ø)		Carriedforward from 62d6012
rocFFT	47.16% <ø> (ø)		Carriedforward from 62d6012
rocRAND	56.90% <ø> (ø)		Carriedforward from 62d6012
rocSOLVER	76.83% <ø> (ø)		Carriedforward from 62d6012
rocSPARSE	74.61% <ø> (ø)		Carriedforward from 62d6012
rocThrust	91.60% <ø> (ø)		Carriedforward from 62d6012

*This pull request uses carry forward flags. Click here to find out more.

Files with missing lines	Coverage Δ
...laslt/tensilelite/Tensile/AsmAddressCalculation.py	61.31% <ø> (ø)
...slt/tensilelite/Tensile/Common/GlobalParameters.py	95.79% <ø> (ø)
...t/tensilelite/Tensile/Common/RequiredParameters.py	100.00% <ø> (ø)
...aslt/tensilelite/Tensile/Common/ValidParameters.py	100.00% <ø> (ø)
...lt/tensilelite/Tensile/SolutionStructs/Solution.py	58.86% <100.00%> (ø)
...tensilelite/Tensile/Components/GlobalWriteBatch.py	69.42% <0.00%> (-0.06%)	⬇️
...blaslt/tensilelite/Tensile/KernelWriterAssembly.py	70.32% <0.00%> (-0.03%)	⬇️

... and 3 files with indirect coverage changes

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[hcman2]

ok if test passed

[assistant-librarian]

TheRock Submodule Bump Activity

Newest first

• 2026-09-17 — Included in TheRock via ROCm/TheRock#8289.