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Fix for RPP HOST output buffer overrun with NCHW to NHWC conversion #11394

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Merged
msiddaiah merged 12 commits into from
Sep 2, 2026
Merged

Fix for RPP HOST output buffer overrun with NCHW to NHWC conversion #11394

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2e63d56
Fix for RPP HOST output buffer overrun with NCHW to NHWC conversion
Aug 27, 2026
8a2b091
simd data store using utility functions instead of raw pointers deref…
Aug 28, 2026
1aabf39
Fix for pre-commit clang-format
Aug 28, 2026
79ae4da
Merge branch 'develop' into users/msiddaia/rpp_host_pln3_pkd3
kiritigowda Aug 31, 2026
2e3dbd5
Merge branch 'develop' into users/msiddaia/rpp_host_pln3_pkd3
msiddaiah Sep 1, 2026
138dfc1
Optimized store24 and store48 for F16 data type with PLN3 to PKD3 con…
Sep 2, 2026
b730567
Fix for pre-commit
Sep 2, 2026
4c5d9d5
Merge branch 'develop' into users/msiddaia/rpp_host_pln3_pkd3
LakshmiKumar23 Sep 2, 2026
ae70050
Merge branch 'develop' into users/msiddaia/rpp_host_pln3_pkd3
LakshmiKumar23 Sep 2, 2026
b1c31f8
Optimized store for f32 pln3 to pkd3 conversion
Sep 2, 2026
d879105
Fix clang-format for F32 PKD3 store optimization
Sep 2, 2026
30ed607
Merge branch 'develop' into users/msiddaia/rpp_host_pln3_pkd3
msiddaiah Sep 2, 2026
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60 changes: 41 additions & 19 deletions projects/rpp/src/include/common/cpu/rpp_cpu_simd_load_store.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1884,7 +1884,8 @@ inline void rpp_store48_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
_mm_storeu_si128((__m128i*)dstPtr, px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 3), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 6), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 9), px128[3]);
_mm_storel_epi64((__m128i*)(dstPtr + 9), px128[3]);
rpp_storeu_si32(dstPtr + 11, _mm_srli_si128(px128[3], 8));
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Resolved

p128[0] = _mm256_extractf128_ps(p[0], 1);
p128[1] = _mm256_extractf128_ps(p[2], 1);
Expand All @@ -1897,7 +1898,8 @@ inline void rpp_store48_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
_mm_storeu_si128((__m128i*)(dstPtr + 12), px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 15), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 18), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 21), px128[3]);
_mm_storel_epi64((__m128i*)(dstPtr + 21), px128[3]);
rpp_storeu_si32(dstPtr + 23, _mm_srli_si128(px128[3], 8));

p128[0] = _mm256_extractf128_ps(p[1], 0);
p128[1] = _mm256_extractf128_ps(p[3], 0);
Expand All @@ -1910,7 +1912,8 @@ inline void rpp_store48_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
_mm_storeu_si128((__m128i*)(dstPtr + 24), px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 27), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 30), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 33), px128[3]);
_mm_storel_epi64((__m128i*)(dstPtr + 33), px128[3]);
rpp_storeu_si32(dstPtr + 35, _mm_srli_si128(px128[3], 8));

p128[0] = _mm256_extractf128_ps(p[1], 1);
p128[1] = _mm256_extractf128_ps(p[3], 1);
Expand All @@ -1923,7 +1926,8 @@ inline void rpp_store48_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
_mm_storeu_si128((__m128i*)(dstPtr + 36), px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 39), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 42), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 45), px128[3]);
_mm_storel_epi64((__m128i*)(dstPtr + 45), px128[3]);
rpp_storeu_si32(dstPtr + 47, _mm_srli_si128(px128[3], 8));
}

inline void rpp_load48_u8pln3_to_f32pln3_avx(Rpp8u* srcPtrR, Rpp8u* srcPtrG, Rpp8u* srcPtrB,
Expand Down Expand Up @@ -2083,9 +2087,11 @@ inline void rpp_store48_f32pln3_to_u8pkd3_avx(Rpp8u* dstPtr, __m256* p) {
_mm_storeu_si128(
(__m128i*)(dstPtr + 24),
px[2]); /* store [R09|G09|B09|R10|G10|B10|R11|G11|B11|R12|G12|B12|00|00|00|00] */
_mm_storeu_si128(
(__m128i*)(dstPtr + 36),
px[3]); /* store [R13|G13|B13|R14|G14|B14|R15|G15|B15|R16|G16|B16|00|00|00|00] */
// Fixed: Only store 12 bytes (not 16) to avoid writing beyond 48-byte boundary
_mm_storel_epi64((__m128i*)(dstPtr + 36),
px[3]); /* store first 8 bytes [R13|G13|B13|R14|G14|B14|R15|G15] */
rpp_storeu_si32(dstPtr + 44,
_mm_srli_si128(px[3], 8)); /* store last 4 bytes [B15|R16|G16|B16] */
}

inline void rpp_load24_u8pln3_to_f64pln3_avx(Rpp8u* srcPtrR, Rpp8u* srcPtrG, Rpp8u* srcPtrB,
Expand Down Expand Up @@ -2596,7 +2602,9 @@ inline void rpp_store24_f32pln3_to_f32pkd3_avx(Rpp32f* dstPtr, __m256* p) {
_mm_storeu_ps(dstPtr + 12, p128[0]);
_mm_storeu_ps(dstPtr + 15, p128[1]);
_mm_storeu_ps(dstPtr + 18, p128[2]);
_mm_storeu_ps(dstPtr + 21, p128[3]);
// Fixed: Only store 3 floats (not 4) to avoid writing beyond 24-float (96-byte) boundary
rpp_storeu_si64(dstPtr + 21, _mm_castps_si128(p128[3])); /* store first 2 floats [R08|G08] */
dstPtr[23] = _mm_cvtss_f32(_mm_movehl_ps(p128[3], p128[3])); /* store 3rd float [B08] */
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}

inline void extract_and_convert_to_f64_pln3_to_pln3(__m256* px, __m256d* p) {
Expand Down Expand Up @@ -3053,9 +3061,11 @@ inline void rpp_store48_f32pln3_to_i8pkd3_avx(Rpp8s* dstPtr, __m256* p) {
_mm_storeu_si128(
(__m128i*)(dstPtr + 24),
px[2]); /* store [R09|G09|B09|R10|G10|B10|R11|G11|B11|R12|G12|B12|00|00|00|00] */
_mm_storeu_si128(
(__m128i*)(dstPtr + 36),
px[3]); /* store [R13|G13|B13|R14|G14|B14|R15|G15|B15|R16|G16|B16|00|00|00|00] */
// Fixed: Only store 12 bytes (not 16) to avoid writing beyond 48-byte boundary
_mm_storel_epi64((__m128i*)(dstPtr + 36),
px[3]); /* store first 8 bytes [R13|G13|B13|R14|G14|B14|R15|G15] */
rpp_storeu_si32(dstPtr + 44,
_mm_srli_si128(px[3], 8)); /* store last 4 bytes [B15|R16|G16|B16] */
}

inline void rpp_load24_i8pln3_to_f64pln3_avx(Rpp8s* srcPtrR, Rpp8s* srcPtrG, Rpp8s* srcPtrB,
Expand Down Expand Up @@ -4749,10 +4759,16 @@ inline void rpp_store24_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
px128[1] = _mm_cvtps_ph(p128[1], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
px128[2] = _mm_cvtps_ph(p128[2], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
px128[3] = _mm_cvtps_ph(p128[3], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
_mm_storeu_si128((__m128i*)dstPtr, px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 3), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 6), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 9), px128[3]);
// Each px128[i] contains [Ri, Gi, Bi, unused] - use overlapping 32-bit stores to write [R,G]
// then [G,B]
rpp_storeu_si32(dstPtr + 0, px128[0]); // Store R0, G0
rpp_storeu_si32(dstPtr + 1, _mm_srli_si128(px128[0], 2)); // Store G0, B0 (G0 overlaps)
rpp_storeu_si32(dstPtr + 3, px128[1]); // Store R1, G1
rpp_storeu_si32(dstPtr + 4, _mm_srli_si128(px128[1], 2)); // Store G1, B1 (G1 overlaps)
rpp_storeu_si32(dstPtr + 6, px128[2]); // Store R2, G2
rpp_storeu_si32(dstPtr + 7, _mm_srli_si128(px128[2], 2)); // Store G2, B2 (G2 overlaps)
rpp_storeu_si32(dstPtr + 9, px128[3]); // Store R3, G3
rpp_storeu_si32(dstPtr + 10, _mm_srli_si128(px128[3], 2)); // Store G3, B3 (G3 overlaps)

p128[0] = _mm256_extractf128_ps(p[0], 1);
p128[1] = _mm256_extractf128_ps(p[1], 1);
Expand All @@ -4763,10 +4779,16 @@ inline void rpp_store24_f32pln3_to_f16pkd3_avx(Rpp16f* dstPtr, __m256* p) {
px128[1] = _mm_cvtps_ph(p128[1], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
px128[2] = _mm_cvtps_ph(p128[2], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
px128[3] = _mm_cvtps_ph(p128[3], _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
_mm_storeu_si128((__m128i*)(dstPtr + 12), px128[0]);
_mm_storeu_si128((__m128i*)(dstPtr + 15), px128[1]);
_mm_storeu_si128((__m128i*)(dstPtr + 18), px128[2]);
_mm_storeu_si128((__m128i*)(dstPtr + 21), px128[3]);
// Each px128[i] contains [Ri, Gi, Bi, unused] - use overlapping 32-bit stores to write [R,G]
// then [G,B]
rpp_storeu_si32(dstPtr + 12, px128[0]); // Store R4, G4
rpp_storeu_si32(dstPtr + 13, _mm_srli_si128(px128[0], 2)); // Store G4, B4 (G4 overlaps)
rpp_storeu_si32(dstPtr + 15, px128[1]); // Store R5, G5
rpp_storeu_si32(dstPtr + 16, _mm_srli_si128(px128[1], 2)); // Store G5, B5 (G5 overlaps)
rpp_storeu_si32(dstPtr + 18, px128[2]); // Store R6, G6
rpp_storeu_si32(dstPtr + 19, _mm_srli_si128(px128[2], 2)); // Store G6, B6 (G6 overlaps)
rpp_storeu_si32(dstPtr + 21, px128[3]); // Store R7, G7
rpp_storeu_si32(dstPtr + 22, _mm_srli_si128(px128[3], 2)); // Store G7, B7 (G7 overlaps)
}

inline void rpp_store8_f32pln1_to_f16pln1_avx(Rpp16f* dstPtr, __m256 p) {
Expand Down
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