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docs(rocke): document C++ touchpoints for adding an IR op - #10801
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Expand dsl_docs/development/extending.md section 1 with the full C++ side of adding an IR op: the rocke_b_<op> builder, the rocke_opcode_t enum, and the three parallel per-opcode tables (rocke_opcode_names[], rocke_opcode_pure[], and the verify.cpp arity classifier) that must stay in enumerator order. Correct the purity description to reflect the PURE_OP_NAMES allowlist model, and fix stale example paths (example/ck_tile/dsl -> python/rocke/examples). JIRA ID : AICK-1711 Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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cgmillette
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lgtm - would like second opinion from @yraparti
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Pull request overview
Updates Rocke DSL extension documentation to better describe the end-to-end steps for adding a new IR op, including the C++ engine touchpoints and parity expectations between Python/C++ lowering paths.
Changes:
- Expands “Adding a New IR Operation” with a 7-touchpoint checklist, including C++ IRBuilder/opcode table requirements and byte-identity parity expectations.
- Clarifies purity behavior as an allowlist (
PURE_OP_NAMES) with a C++ mirror (rocke_opcode_pure[]). - Updates stale example path references from
example/ck_tile/dsl/...topython/rocke/examples/....
Suppressed comments (1)
dnn-providers/hip-kernel-provider/rocke/platform/dsl_docs/development/extending.md:289
- Similarly, this parity-example instruction still points to a
python/rocke/examples/<NN>_my_op/gen.pygenerator script. The existingpython/rocke/examples/layout is module-based (e.g.common/*.py) and usesrun_all.py+_goldens/rather than per-examplegen.pyentrypoints. Updating this reference to the current examples registration mechanism would avoid sending contributors to create files in a pattern that the repo doesn’t currently use.
### 3.9 Optional CK Tile parity example
For end-to-end gating, add `python/rocke/examples/<NN>_my_op/gen.py`:
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LGTM with minor nits. What’s goodFills a real gap. The old doc stopped at Python Purity correction is accurate. The old text implied side-effecting ops were inferred by default. The new allowlist model matches the code: def is_pure(self) -> bool:
if "pure" in self.attrs:
return bool(self.attrs["pure"])
return is_pure_op_name(self.name)Opcode-table warning is well grounded. Seven-touchpoint checklist gives a practical ordering: Python builder → C++ builder/tables → dual LLVM lowerers → optional HIP → serialization → tests/byte-identity. Examples and API references check out: Nits / suggestions1. §1.2 cross-references §1.4 for byte-identity Two places say “byte-identity differential (§1.4)” when talking about C++ IRBuilder authoring. §1.4 is LLVM lowering; byte-identity is §1.6 / touchpoint 7. §1.4 does mention byte-identity, but the C++-builder context is really “both engines must author the op before lowering can be compared.” Point to §1.6 (or touchpoint 7) instead. 2. Section 3 example paths are still stale The PR updates
Either keep this PR scoped to §1 (strongest part), or align §3 with the real layout and note whether 3. Optional: mention the opcode alignment test Worth a one-liner that 4. Optional: Python textual printer §1.3 ( Accuracy spot-check (code vs doc)
Recommendation: Merge for §1. Consider a follow-up (or a small edit in this PR) for the §1.2 cross-ref and §3 example-path accuracy. |
yraparti
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address nit in a different ticket.
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Will address nit in AICK-2246 |
TheRock Submodule Bump ActivityNewest first
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Expand dsl_docs/development/extending.md section 1 with the full C++ side of adding an IR op: the rocke_b_ builder, the rocke_opcode_t enum, and the three parallel per-opcode tables (rocke_opcode_names[], rocke_opcode_pure[], and the verify.cpp arity classifier) that must stay in enumerator order. Correct the purity description to reflect the PURE_OP_NAMES allowlist model, and fix stale example paths (example/ck_tile/dsl -> python/rocke/examples).
JIRA ID : AICK-1711