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[hipblaslt] Equality tuning for BF16, MXF8, MXF4, F8 MAF - #10250

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AmosLewis merged 4 commits into
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users/minsukim/gfx1250_equality_maf_20260731
Aug 10, 2026
Merged

AmosLewis merged 4 commits into
developfrom
users/minsukim/gfx1250_equality_maf_20260731

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@minsukim-amd

@minsukim-amd minsukim-amd commented Jul 31, 2026 •

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Motivation

Measure MAF for various datatypes

Technical Details

Equality tuning for 4K x 4K x 65536 shape

Added 4 liblogic yaml files for each BBS_TN, F8F8S_TN, MX_F8BS_TN, MX_F4BS_TN

Test Plan

Tested with tensilelite and hipblaslt-bench verification run

Test Result

Passed

Submission Checklist

JIRA ID : AIHPBLAS-4151

@therock-pr-bot

therock-pr-bot Bot commented Jul 31, 2026 •

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✅ All Checks Passed — Ready for Review

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📝 PR Description ✅ Pass —
⛔ Forbidden Files ✅ Pass —
🧪 Unit Test ✅ Pass PR does not contain code files — Unit Test auto-passed
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🤖 therock-pr-bot ✅ Pass —

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therock-pr-bot Bot commented Jul 31, 2026 •

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🎉 All checks passed! This PR is ready for review.

@codecov

codecov Bot commented Aug 1, 2026 •

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Codecov Report

✅ All modified and coverable lines are covered by tests.

Additional details and impacted files
@@             Coverage Diff             @@
##           develop   #10250      +/-   ##
===========================================
- Coverage    68.93%   68.78%   -0.16%     
===========================================
  Files         2762     2741      -21     
  Lines       455034   451375    -3659     
  Branches     67122    66507     -615     
===========================================
- Hits        313673   310442    -3231     
+ Misses      118430   118285     -145     
+ Partials     22931    22648     -283     
Flag Coverage Δ *Carryforward flag
TensileLite-CPP 38.13% <ø> (+0.07%) ⬆️ Carriedforward from ff8d042
TensileLite-Unit 64.88% <ø> (-11.06%) ⬇️ Carriedforward from ff8d042
hipBLAS 90.62% <ø> (ø) Carriedforward from ff8d042
hipBLASLt 34.89% <ø> (ø)
hipCUB 83.47% <ø> (ø) Carriedforward from ff8d042
hipDNN 86.39% <ø> (-0.13%) ⬇️ Carriedforward from ff8d042
hipFFT 47.34% <ø> (-0.40%) ⬇️ Carriedforward from ff8d042
hipRAND 76.12% <ø> (ø) Carriedforward from ff8d042
hipSOLVER 69.18% <ø> (+0.15%) ⬆️ Carriedforward from ff8d042
hipSPARSE 86.27% <ø> (ø) Carriedforward from ff8d042
rocBLAS 47.95% <ø> (-0.28%) ⬇️ Carriedforward from ff8d042
rocFFT 47.61% <ø> (-1.04%) ⬇️ Carriedforward from ff8d042
rocRAND 57.03% <ø> (+0.01%) ⬆️ Carriedforward from ff8d042
rocSOLVER 76.92% <ø> (ø) Carriedforward from ff8d042
rocSPARSE 72.59% <ø> (+0.04%) ⬆️ Carriedforward from ff8d042
rocThrust 91.60% <ø> (ø) Carriedforward from ff8d042

*This pull request uses carry forward flags. Click here to find out more.
see 141 files with indirect coverage changes

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@AmosLewis

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Merging this with --admin for the BKC release code cut-off. Rationale, so the bypass is on the record:

Both attempt-2 re-runs are done — TheRock CI https://github.com/ROCm/rocm-libraries/actions/runs/31159672227 and TheRock Multi-Arch CI https://github.com/ROCm/rocm-libraries/actions/runs/31159672377. Math CI Summary and pre-commit (the other two required contexts) are green, @babakpst approved, no unresolved review threads. All three reds inside the required TheRock CI Summary are known infra:

Red check Keypoint
rocjitsu race check (gfx94X and gfx950) Exits ~50 s in on OpenMP runtime not found: .../lib/x86_64-unknown-linux-gnu/libomp.so. Fixed on develop by #10522 (Aug 9 17:59 UTC). This run was created Aug 7 07:56 UTC, so it replays a pre-fix merge SHA — no re-run can pick the fix up
Build (gfx125X-dcgpu) 30-minute Fetch sources timeout cloning compiler/amd-llvm (ROCm/TheRock#7170), third consecutive occurrence. Control in the same run: Build (gfx950-dcgpu) failed identically on attempt 1 and came back green on attempt 2 at 17:58 UTC — same commit, same diff, so this is the clone throttling, not the YAML
Test RPM Install - sles16, Multi-Arch CI Summary, codecov/project/hipBLASLt Outside the required set. sles16 is ROCm/TheRock#7161; codecov/patch is green

What I am not signing off on: gfx125X-dcgpu is the gfx1250 family, so no CI lane ever built the arch these logic files target — that evidence is the author's tensilelite / hipblaslt-bench verification run, and gfx1250 has no test hardware in the matrix anyway. I am accepting that gap because hipBLASLt's device-library codegen filters logic files by ARCHES, so gfx1250_*_UserArgs.yaml is not read by a gfx942 / gfx950 / gfx1151 build — the only lane that can regress from this diff is the gfx125X one that ROCm/TheRock#7170 is already blocking. I am also not signing off on gfx1250 numerics or performance.

Why not just wait: rocjitsu needs a new merge base rather than a re-run, and gfx125X has hit #7170 three times out of three, so another round would not reliably produce the gfx1250 build result either.

@AmosLewis
AmosLewis merged commit 3a08f1b into develop Aug 10, 2026
241 of 258 checks passed
assistant-librarian Bot pushed a commit to ROCm/hipBLASLt that referenced this pull request Aug 10, 2026
[hipblaslt] Equality tuning for BF16, MXF8, MXF4, F8 MAF
 (#10250)

Equality tuning for 4K x 4K x 65536 shape.

Added 4 liblogic yaml files for each BBS_TN, F8F8S_TN, MX_F8BS_TN, MX_F4BS_TN.

Tested with tensilelite and hipblaslt-bench verification run.

Merged with --admin for the BKC release code cut-off. Math CI Summary and
pre-commit green; the reds in TheRock CI Summary are ROCm/rocm-libraries#10522
(rocjitsu libomp.so, fixed on develop after this run was created) and
ROCm/TheRock#7170 (30-min amd-llvm clone timeout on gfx125X, with a same-run
green gfx950 build as control). Rationale in the PR thread.

JIRA ID : AIHPBLAS-4151
@AmosLewis

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Closing the loop on the one gap I flagged when merging this: gfx1250 now has a real build.

The develop post-merge run on the squash commit 3a08f1b4 built the lane that never completed pre-merge — Build (gfx125X-dcgpu) succeeded in 24 minutes (01:35 → 01:59 UTC), no Fetch sources timeout this time: https://github.com/ROCm/rocm-libraries/actions/runs/31442355323/job/93629787695

So the git apply-clean assumption held and the four gfx1250/Equality/*_UserArgs.yaml files compile on the arch they target. Zero failing jobs in that run so far. The downstream Test (gfx125X-dcgpu) jobs are skipped, which is expected — there is no gfx1250 test hardware in the matrix — so runtime behaviour still rests on your tensilelite / hipblaslt-bench verification, exactly as stated above.

Also confirmed: the subrepo mirror landed in ROCm/hipBLASLt develop as 08afa04e5 with your authorship and the JIRA ID line intact.

tony-davis pushed a commit that referenced this pull request Aug 29, 2026
…ers (#11442)

JIRA ID : AIHPBLAS-4531
GitHub ID: #11397 

## Motivation


`Tensile/Tests/unit/test_PlaceholderMerge.py::test_logic_yaml_sibling_device_names_consistent`
is currently **failing on `develop`**, turning CI red for unrelated
hipBLASLt PRs (observed on #10941 among others). This PR fixes the
underlying data divergence so the shared CI lane goes green again.

The test asserts that library-logic YAMLs sharing a basename within one
architecture directory all declare the same `DeviceNames` header. Four
gfx1250 `Equality/` basenames declared `- [Device 73f0, Device 0073,
Device 75c1]` while their `GridBased/` and `Origami/` siblings declared
`[Device 73f0]`.

Provenance: the 3-ID list was introduced by `3a08f1b4d94` (#10250, a
tuning PR whose description never mentions device IDs, admin-merged with
partial CI) and never propagated to the sibling trees — 208 of the 212
files in each affected arch directory use `[Device 73f0]`. The
divergence has existed since then but was invisible to CI. `134466bcb4a`
(#11274) later re-nested the tree (`asm_full/gfx1250/Equality/` ->
`asm_full/gfx1250/gfx1250/Equality/`), which caused the test's
`_iter_arch_dirs()` to start descending into that directory and
**surfaced** the pre-existing drift. #11274 is not the cause — the
divergence is verifiably present at `134466bcb4a^`.

## Technical Details

**Commit 1 — normalize the data (8 files).** Four basenames x the
`gfx1250` and `gfx1250v0` trees = 8 `Equality/` YAMLs narrowed from `-
[Device 73f0, Device 0073, Device 75c1]` to `- [Device 73f0]`, matching
their siblings.

Narrowing 8 files was chosen over widening the 416 siblings to two
additional IDs of unknown provenance (see the open question below).

**Why this is functionally safe.** `DeviceNames` entries are PCIe chip
IDs consumed to emit a runtime `PciChipId` hardware predicate — but only
where `supportsChipIdPredicate()` is true, which is `gfx950` and nothing
else:

- `tensilelite/Tensile/Common/Architectures.py:180-186`
- mirrored in C++ at
`tensilelite/include/Tensile/AMDGPUPredicates.hpp:53-56`

On gfx1250 the field is parsed and then dropped: no `PciChipId`
predicate is emitted and no `_ID` filename suffix is generated. It is
inert for kernel selection on this architecture, so no GPU sees a
different kernel set as a result of this change. The value does remain
live in the Python solution de-duplication key
(`Tensile/SolutionStructs/Solution.py:6193-6205`, which is not
arch-gated) — which is exactly why keeping it consistent across siblings
matters.

**Commit 2 — close a test blind spot (separate concern, 1 file).**
`_DEVICE_NAMES_RE` in `test_PlaceholderMerge.py` matched only the
positional list form (`- [Device ...]`) and silently skipped the mapping
form (`DeviceNames: [Device ...]`) used by Origami logic files. The
regex now matches both. This is a genuine coverage gap, not cosmetic:
one of the four basenames (`*_BBS_BH_Bias_HA_S_SAV_UserArgs.yaml`)
diverges only against a mapping-form Origami sibling and was therefore
invisible to the old test. Parse coverage over the `asm_full/` tree goes
from **1840/1936 to 1936/1936** files.

## Test Plan

Regression coverage is the pre-existing shared-CI unit test itself —
this is the test that is red on `develop`, so the fix is validated by
the same lane that caught it (`test_PlaceholderMerge.py` matches the
`test_*` pattern picked up by the Libraries PR Bot unit-test check).

Run locally with `rocisa` built via `tlbuild` into `build_tmp` and
executed through a `tlrun`-style `PYTHONPATH` (nothing pip-installed):

```bash
pytest projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_PlaceholderMerge.py
pytest projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_PlaceholderMerge.py::test_logic_yaml_sibling_device_names_consistent
```

Control run: the same test executed against the pre-fix YAML content, to
confirm it actually detects the condition rather than passing vacuously.

## Test Result

- `test_logic_yaml_sibling_device_names_consistent` — **PASSED**.
- Full `test_PlaceholderMerge.py` — **22 passed**.
- Control run against pre-fix data — **failed as expected**, with
`AssertionError: Divergent sibling DeviceNames` listing both `*_BBS_*`
pairs. Confirms the assertion is live and the widened regex is what
surfaces the second pair.
- Post-rebase scan of the whole `asm_full/` tree (replicating
`_iter_arch_dirs` + `_read_device_names` + the grouping assert): **1936
YAML files walked, 1936 with `DeviceNames` parsed, 0 violations.**
Re-run after rebasing onto current `origin/develop` to confirm no
newly-landed YAMLs reintroduce divergence.
- Branch rebased onto current `origin/develop` (clean, no conflicts) per
the `hipblaslt-pr-quality` stale-base rule for
validator-vs-validated-data changes.
- Automated GitHub checks are pending.

## Submission Checklist

- [x] Look over the contributing guidelines at
https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

## Risk level

**Low (1/5).** Eight data files change a field that is provably inert on
the only architecture they apply to (`supportsChipIdPredicate()` is
gfx950-only), plus one widened regex in a host-side unit test. No kernel
source, no build output, no host library code, no public API. The change
makes 8 files agree with the 208 already-consistent files in the same
directory.
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