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7 changes: 6 additions & 1 deletion README.md
Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,12 @@ requirements.txt Python packages for pytest and corpus helpers.
- `corpus/kernels/`: standalone HIP kernel reproducers. Current backends include
`hip-stream-k`, `hip-matmul`, `hipkittens`, and `rocblas`.
- `corpus/cts/`: HIP semantic tests organized by target family, including
FPSan-derived floating-point cases and standalone integer ISA cases.
FPSan-derived floating-point cases and standalone integer ISA cases. The
gfx1250 integer suite covers the portable RDNA4 integer families, both
gfx1250 integer matrix forms, and selected gfx1250-specific instructions. Its
build-time coverage gate extracts the gfx1250 image from each linked test
executable and verifies that every expected opcode is present in the code
that the runtime test executes.
- `corpus/semantics/`: standalone HIP programs with deterministic inputs,
source-ISA coverage, and typed results that can be captured under any
externally selected launch configuration.
Expand Down
67 changes: 63 additions & 4 deletions corpus/cts/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,7 @@ set(CTS_HAS_RDNA3 OFF)
set(CTS_HAS_GFX12 OFF)

foreach(hip_arch IN LISTS CMAKE_HIP_ARCHITECTURES)
if(hip_arch MATCHES "^gfx125")
if(hip_arch STREQUAL "gfx1250")
set(CTS_HAS_GFX1250 ON)
endif()
if(hip_arch MATCHES "^gfx11")
Expand Down Expand Up @@ -636,7 +636,7 @@ if(CTS_HAS_RDNA4)
cts_add_hip_test(int_isa_rdna4_bit_permute_test
"${CTS_TEST_CASES_DIR}/general/int_isa/bit_permute_test.cpp")
cts_add_hip_test(int_isa_rdna4_integer_dot_test
"${CTS_TEST_CASES_DIR}/rdna4/int_isa/integer_dot_test.cpp")
"${CTS_TEST_CASES_DIR}/general/int_isa/integer_dot_test.cpp")
cts_add_hip_test(int_isa_rdna4_packed_convert_test
"${CTS_TEST_CASES_DIR}/general/int_isa/packed_convert_test.cpp")

Expand All @@ -645,7 +645,7 @@ if(CTS_HAS_RDNA4)
cts_add_rdna4_wave_mode_tests(mbcnt
"${CTS_TEST_CASES_DIR}/general/int_isa/mbcnt_test.cpp")
cts_add_rdna4_wave_mode_tests(ds_permute
"${CTS_TEST_CASES_DIR}/rdna4/int_isa/ds_permute_test.cpp")
"${CTS_TEST_CASES_DIR}/general/int_isa/ds_permute_test.cpp")
# Fetch-invalid semantics require the per-lane source value to remain in a
# VGPR across an EXEC-divergent region. At -O0 clang outlines the trait and
# reloads that value from scratch only for active lanes, defeating the ISA
Expand All @@ -657,7 +657,7 @@ if(CTS_HAS_RDNA4)
cts_add_rdna4_wave_mode_tests(dpp
"${CTS_TEST_CASES_DIR}/general/int_isa/dpp_test.cpp")
cts_add_rdna4_wave_mode_tests(permlane
"${CTS_TEST_CASES_DIR}/rdna4/int_isa/permlane_test.cpp")
"${CTS_TEST_CASES_DIR}/general/int_isa/permlane_test.cpp")
cts_add_rdna4_wave_mode_tests(ballot
"${CTS_TEST_CASES_DIR}/general/int_isa/ballot_test.cpp")
cts_add_rdna4_wave_mode_tests(compare
Expand All @@ -678,3 +678,62 @@ if(CTS_HAS_RDNA4)
cts_add_rdna4_wave_mode_tests(swmmac_i32_16x16x64_iu4
"${CTS_TEST_CASES_DIR}/rdna4/int_isa/swmmac_i32_16x16x64_iu4_test.cpp")
endif()

if(CTS_HAS_GFX1250)
find_package(Python3 REQUIRED COMPONENTS Interpreter)
if(NOT CMAKE_OBJDUMP)
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message(FATAL_ERROR "gfx1250 linked-image coverage requires CMAKE_OBJDUMP")
endif()

set(GFX1250_INT_ISA_COVERAGE_MANIFEST
"${CMAKE_CURRENT_LIST_DIR}/int_isa_gfx1250_coverage.json")
set(GFX1250_INT_ISA_COVERAGE_SCRIPT
"${CMAKE_CURRENT_LIST_DIR}/scripts/check_int_isa_coverage.py")
set(GFX1250_INT_ISA_CASE_INVENTORY
"${CTS_TEST_CASES_DIR}/int_isa_test_cases.json")
set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS
"${GFX1250_INT_ISA_COVERAGE_MANIFEST}")
file(READ "${GFX1250_INT_ISA_COVERAGE_MANIFEST}"
GFX1250_INT_ISA_COVERAGE_JSON)
string(JSON GFX1250_INT_ISA_TEST_COUNT LENGTH
"${GFX1250_INT_ISA_COVERAGE_JSON}" tests)
math(EXPR GFX1250_INT_ISA_LAST_TEST "${GFX1250_INT_ISA_TEST_COUNT} - 1")
set(GFX1250_INT_ISA_TARGETS)
set(GFX1250_INT_ISA_IMAGE_ARGS)
foreach(test_index RANGE ${GFX1250_INT_ISA_LAST_TEST})
string(JSON target_name GET "${GFX1250_INT_ISA_COVERAGE_JSON}"
tests ${test_index} name)
string(JSON source GET "${GFX1250_INT_ISA_COVERAGE_JSON}"
tests ${test_index} source)
cts_add_hip_test(${target_name} "${CTS_TEST_CASES_DIR}/${source}")
list(APPEND GFX1250_INT_ISA_TARGETS ${target_name})
list(APPEND GFX1250_INT_ISA_IMAGE_ARGS
--image "${target_name}=$<TARGET_FILE:${target_name}>")
endforeach()

# Fetch-invalid semantics require the per-lane source value to remain in a
# VGPR across an EXEC-divergent region. See the RDNA4 targets above.
target_compile_options(int_isa_gfx1250_ds_permute_test PRIVATE -O2)
add_custom_target(int_isa_gfx1250_source_coverage_test ALL
COMMAND "${Python3_EXECUTABLE}"
"${GFX1250_INT_ISA_COVERAGE_SCRIPT}"
--coverage "${GFX1250_INT_ISA_COVERAGE_MANIFEST}"
--case-inventory "${GFX1250_INT_ISA_CASE_INVENTORY}"
--source-root "${CTS_TEST_CASES_DIR}"
--llvm-objdump "${CMAKE_OBJDUMP}"
${GFX1250_INT_ISA_IMAGE_ARGS}
DEPENDS
${GFX1250_INT_ISA_TARGETS}
"${GFX1250_INT_ISA_COVERAGE_MANIFEST}"
"${GFX1250_INT_ISA_CASE_INVENTORY}"
"${GFX1250_INT_ISA_COVERAGE_SCRIPT}"
VERBATIM)
add_test(NAME int_isa_gfx1250_source_coverage_test
COMMAND "${Python3_EXECUTABLE}"
"${GFX1250_INT_ISA_COVERAGE_SCRIPT}"
--coverage "${GFX1250_INT_ISA_COVERAGE_MANIFEST}"
--case-inventory "${GFX1250_INT_ISA_CASE_INVENTORY}"
--source-root "${CTS_TEST_CASES_DIR}"
--llvm-objdump "${CMAKE_OBJDUMP}"
${GFX1250_INT_ISA_IMAGE_ARGS})
endif()
158 changes: 158 additions & 0 deletions corpus/cts/int_isa_gfx1250_coverage.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,158 @@
{
"schema_version": 2,
"target": "gfx1250",
"scope": "RDNA4-parity integer semantic families that compile for gfx1250, both gfx1250 integer matrix instructions, and selected gfx1250-specific integer instructions. Expected opcodes are checked in the linked runtime images.",
"tests": [
{
"name": "int_isa_gfx1250_bitfield_test",
"source": "general/int_isa/bitfield_test.cpp",
"expected_opcodes": ["v_bfe_i32", "v_bfe_u32"]
},
{
"name": "int_isa_gfx1250_lerp_test",
"source": "general/int_isa/lerp_test.cpp",
"expected_opcodes": ["v_lerp_u8"]
},
{
"name": "int_isa_gfx1250_packed_sad_test",
"source": "general/int_isa/packed_sad_test.cpp",
"expected_opcodes": [
"v_sad_u8",
"v_sad_hi_u8",
"v_sad_u16",
"v_msad_u8",
"v_qsad_pk_u16_u8",
"v_mqsad_pk_u16_u8",
"v_mqsad_u32_u8"
]
},
{
"name": "int_isa_gfx1250_bit_permute_test",
"source": "general/int_isa/bit_permute_test.cpp",
"expected_opcodes": ["v_alignbit_b32", "v_alignbyte_b32", "v_perm_b32"]
},
{
"name": "int_isa_gfx1250_integer_dot_test",
"source": "general/int_isa/integer_dot_test.cpp",
"expected_opcodes": [
"v_dot4_i32_iu8",
"v_dot4_u32_u8",
"v_dot8_i32_iu4",
"v_dot8_u32_u4"
]
},
{
"name": "int_isa_gfx1250_packed_convert_test",
"source": "general/int_isa/packed_convert_test.cpp",
"expected_opcodes": [
"v_cvt_pk_i16_i32",
"v_cvt_pk_u16_u32",
"v_cvt_pk_norm_i16_f32",
"v_cvt_pk_norm_u16_f32",
"v_cvt_pk_u8_f32"
]
},
{
"name": "int_isa_gfx1250_saturating_pack_test",
"source": "gfx1250/int_isa/saturating_pack_test.cpp",
"expected_opcodes": ["v_sat_pk_u8_i16", "v_sat_pk4_i4_i8", "v_sat_pk4_u4_u8"]
},
{
"name": "int_isa_gfx1250_packed_add_minmax_test",
"source": "gfx1250/int_isa/packed_add_minmax_test.cpp",
"expected_opcodes": [
"v_pk_add_max_i16",
"v_pk_add_max_u16",
"v_pk_add_min_i16",
"v_pk_add_min_u16"
]
},
{
"name": "int_isa_gfx1250_packed_permute_test",
"source": "gfx1250/int_isa/packed_permute_test.cpp",
"expected_opcodes": ["v_perm_pk16_b4_u4", "v_perm_pk16_b6_u4", "v_perm_pk16_b8_u4"]
},
{
"name": "int_isa_gfx1250_relative_move_test",
"source": "gfx1250/int_isa/relative_move_test.cpp",
"expected_opcodes": ["v_movrelsd_b32", "v_movrelsd_2_b32", "v_swaprel_b32"]
},
{
"name": "int_isa_gfx1250_wmma_i32_16x16x64_iu8_test",
"source": "gfx1250/int_isa/wmma_i32_16x16x64_iu8_test.cpp",
"expected_opcodes": ["v_wmma_i32_16x16x64_iu8"]
},
{
"name": "int_isa_gfx1250_swmmac_i32_16x16x128_iu8_test",
"source": "gfx1250/int_isa/swmmac_i32_16x16x128_iu8_test.cpp",
"expected_opcodes": ["v_swmmac_i32_16x16x128_iu8"]
},
{
"name": "int_isa_gfx1250_lane_read_test",
"source": "general/int_isa/lane_read_test.cpp",
"expected_opcodes": ["v_readfirstlane_b32", "v_readlane_b32"]
},
{
"name": "int_isa_gfx1250_mbcnt_test",
"source": "general/int_isa/mbcnt_test.cpp",
"expected_opcodes": ["v_mbcnt_lo_u32_b32"]
},
{
"name": "int_isa_gfx1250_ds_permute_test",
"source": "general/int_isa/ds_permute_test.cpp",
"expected_opcodes": ["ds_bpermute_b32", "ds_bpermute_fi_b32", "ds_permute_b32"]
},
{
"name": "int_isa_gfx1250_ds_swizzle_test",
"source": "general/int_isa/ds_swizzle_test.cpp",
"expected_opcodes": ["ds_swizzle_b32"]
},
{
"name": "int_isa_gfx1250_dpp_test",
"source": "general/int_isa/dpp_test.cpp",
"expected_opcodes": ["v_mov_b32_dpp"]
},
{
"name": "int_isa_gfx1250_permlane_test",
"source": "general/int_isa/permlane_test.cpp",
"expected_opcodes": [
"v_permlane16_b32",
"v_permlane16_var_b32",
"v_permlane64_b32",
"v_permlanex16_b32",
"v_permlanex16_var_b32"
]
},
{
"name": "int_isa_gfx1250_ballot_test",
"source": "general/int_isa/ballot_test.cpp",
"semantic_only": true,
"reason": "The target lowers ballot builtins to EXEC and compare operations rather than a dedicated ballot opcode."
},
{
"name": "int_isa_gfx1250_compare_test",
"source": "general/int_isa/compare_test.cpp",
"expected_opcodes": [
"v_cmp_eq_u32",
"v_cmp_lt_i32",
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"v_cmp_lt_u32",
"v_cmp_ge_i64",
"v_cmp_ge_u64"
]
},
{
"name": "int_isa_gfx1250_reduction_test",
"source": "general/int_isa/reduction_test.cpp",
"expected_opcodes": [
"v_add_nc_u32_dpp",
"v_min_i32_dpp",
"v_max_i32_dpp",
"v_min_u32_dpp",
"v_max_u32_dpp",
"v_and_b32_dpp",
"v_or_b32_dpp",
"v_xor_b32_dpp"
]
}
]
}
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