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Merged
aazz44ss merged 3 commits into from
Dec 1, 2022
Merged

TT logic / fix solutions / optimiza sgpr usage #12

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b385dee
modify TT logic file to support M/N=1
aazz44ss Nov 29, 2022
ad8f026
modify some solutions to reduce sgpr usage
aazz44ss Nov 29, 2022
02c1145
optimize sgpr usage
aazz44ss Nov 30, 2022
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26 changes: 13 additions & 13 deletions ...sile/Logic/asm_full/aldebaran/104CU/GridBased/aldebaran_Cijk_Alik_Bjlk_BBS_BBiasH_AH.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -79,26 +79,26 @@
EdgeType: ShiftPtr
EnableMatrixInstruction: true
ExpandPointerSwap: 0
GlobalLoadVectorWidthA: 4
GlobalLoadVectorWidthB: 4
GlobalLoadVectorWidthA: 1
GlobalLoadVectorWidthB: 1
GlobalReadPerMfma: 1
GlobalReadVectorWidth: 4
GlobalReadVectorWidth: 1
GlobalSplitU: 1
GlobalSplitUAlgorithm: SingleBuffer
GlobalWriteVectorWidth: 1
GroupLoadStore: false
GuaranteeNoPartialA: true
GuaranteeNoPartialB: false
GuaranteeNoPartialB: true
ISA: [9, 0, 10]
InnerUnroll: 1
InterleaveAlpha: 0
KernelLanguage: Assembly
LSCA: 32
LSCB: 32
LSPA: 32
LSPB: 32
LVCA: 8
LVCB: 8
LSPA: 8
LSPB: 8
LVCA: 32
LVCB: 32
LVPA: 8
LVPB: 8
LdsBlockSizePerPad: 128
Expand Down Expand Up @@ -156,12 +156,12 @@
NumElementsPerBatchStore: 2
NumElementsPerThread: 4
NumGlobalWriteVectorsPerThread: 4
NumLoadsA: 1
NumLoadsB: 1
NumLoadsA: 4
NumLoadsB: 4
NumLoadsCoalescedA: 1
NumLoadsCoalescedB: 1
NumLoadsPerpendicularA: 1
NumLoadsPerpendicularB: 1
NumLoadsPerpendicularA: 4
NumLoadsPerpendicularB: 4
NumThreads: 256
OptNoLoadLoop: 1
PackedC0IdxChars: [I]
Expand Down Expand Up @@ -264,7 +264,7 @@
WorkGroupMapping: 8
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: false
_UseSgprForGRO: 1
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down
26 changes: 13 additions & 13 deletions ...sile/Logic/asm_full/aldebaran/104CU/GridBased/aldebaran_Cijk_Alik_Bjlk_HHS_BBiasH_AH.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,26 +79,26 @@
EdgeType: ShiftPtr
EnableMatrixInstruction: true
ExpandPointerSwap: 0
GlobalLoadVectorWidthA: 4
GlobalLoadVectorWidthB: 4
GlobalLoadVectorWidthA: 1
GlobalLoadVectorWidthB: 1
GlobalReadPerMfma: 1
GlobalReadVectorWidth: 4
GlobalReadVectorWidth: 1
GlobalSplitU: 1
GlobalSplitUAlgorithm: SingleBuffer
GlobalWriteVectorWidth: 1
GroupLoadStore: false
GuaranteeNoPartialA: true
GuaranteeNoPartialB: false
GuaranteeNoPartialB: true
ISA: [9, 0, 10]
InnerUnroll: 1
InterleaveAlpha: 0
KernelLanguage: Assembly
LSCA: 32
LSCB: 32
LSPA: 32
LSPB: 32
LVCA: 8
LVCB: 8
LSPA: 8
LSPB: 8
LVCA: 32
LVCB: 32
LVPA: 8
LVPB: 8
LdsBlockSizePerPad: 128
Expand Down Expand Up @@ -156,12 +156,12 @@
NumElementsPerBatchStore: 2
NumElementsPerThread: 4
NumGlobalWriteVectorsPerThread: 4
NumLoadsA: 1
NumLoadsB: 1
NumLoadsA: 4
NumLoadsB: 4
NumLoadsCoalescedA: 1
NumLoadsCoalescedB: 1
NumLoadsPerpendicularA: 1
NumLoadsPerpendicularB: 1
NumLoadsPerpendicularA: 4
NumLoadsPerpendicularB: 4
NumThreads: 256
OptNoLoadLoop: 1
PackedC0IdxChars: [I]
Expand Down Expand Up @@ -264,7 +264,7 @@
WorkGroupMapping: 8
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: false
_UseSgprForGRO: 1
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down
38 changes: 19 additions & 19 deletions ...c/Tensile/Logic/asm_full/aldebaran/104CU/GridBased/aldebaran_Cijk_Alik_Bjlk_SBBias_A.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -79,42 +79,42 @@
EdgeType: ShiftPtr
EnableMatrixInstruction: true
ExpandPointerSwap: 0
GlobalLoadVectorWidthA: 4
GlobalLoadVectorWidthB: 4
GlobalLoadVectorWidthA: 1
GlobalLoadVectorWidthB: 1
GlobalReadPerMfma: 1
GlobalReadVectorWidth: 4
GlobalReadVectorWidth: 1
GlobalSplitU: 1
GlobalSplitUAlgorithm: SingleBuffer
GlobalWriteVectorWidth: 1
GroupLoadStore: false
GuaranteeNoPartialA: true
GuaranteeNoPartialB: false
GuaranteeNoPartialB: true
ISA: [9, 0, 10]
InnerUnroll: 1
InterleaveAlpha: 0
KernelLanguage: Assembly
LSCA: 32
LSCB: 32
LSPA: 32
LSPB: 32
LVCA: 8
LVCB: 8
LSPA: 8
LSPB: 8
LVCA: 32
LVCB: 32
LVPA: 8
LVPB: 8
LdsBlockSizePerPad: 128
LdsBlockSizePerPadA: 128
LdsBlockSizePerPadB: 0
LdsInitCVgprs: false
LdsNumElements: 6400
LdsNumElementsAlignedA: 1280
LdsNumElements: 6208
LdsNumElementsAlignedA: 1088
LdsNumElementsAlignedB: 1024
LdsOffsetA: 0
LdsOffsetA_Blk: 4096
LdsOffsetB: 1280
LdsOffsetB_Blk: 5376
LdsPadA: 8
LdsOffsetB: 1088
LdsOffsetB_Blk: 5184
LdsPadA: 2
LdsPadB: 0
LocalReadVectorWidth: 4
LocalReadVectorWidth: 1
LocalSplitU: 1
LocalWritePerMfma: -1
LocalWriteUseSgprA: false
Expand Down Expand Up @@ -156,12 +156,12 @@
NumElementsPerBatchStore: 2
NumElementsPerThread: 4
NumGlobalWriteVectorsPerThread: 4
NumLoadsA: 1
NumLoadsB: 1
NumLoadsA: 4
NumLoadsB: 4
NumLoadsCoalescedA: 1
NumLoadsCoalescedB: 1
NumLoadsPerpendicularA: 1
NumLoadsPerpendicularB: 1
NumLoadsPerpendicularA: 4
NumLoadsPerpendicularB: 4
NumThreads: 256
OptNoLoadLoop: 1
PackedC0IdxChars: [I]
Expand Down Expand Up @@ -264,7 +264,7 @@
WorkGroupMapping: 8
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: false
_UseSgprForGRO: 1
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 1
Expand Down
28 changes: 14 additions & 14 deletions ...sile/Logic/asm_full/aldebaran/104CU/GridBased/aldebaran_Cijk_Alik_Bljk_BBS_BBiasH_AH.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -25653,7 +25653,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -25666,7 +25666,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -30141,7 +30141,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -30154,7 +30154,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -34101,7 +34101,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -34114,7 +34114,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -37005,7 +37005,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -37018,7 +37018,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -251373,7 +251373,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -251386,7 +251386,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -266157,7 +266157,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -266170,7 +266170,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down Expand Up @@ -269589,7 +269589,7 @@
UnrollMemFence: false
Use64bShadowLimit: 1
UseInstOffsetForGRO: 0
UseSgprForGRO: -1
UseSgprForGRO: 0
Valid: true
VectorAtomicWidth: 1
VectorStore: -1
Expand All @@ -269602,7 +269602,7 @@
WorkGroupMappingType: B
_DepthULds: 32
_GlobalAccumulation: null
_UseSgprForGRO: 1
_UseSgprForGRO: 0
_VectorStore: 1
_WorkspaceSizePerElemC: 0
_staggerStrideShift: 2
Expand Down
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