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[FlyDSL] [MoE] Fix stage-1 grid leaving padded intermediate columns unwritten #6598

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[FlyDSL] [MoE] Fix stage-1 grid leaving padded intermediate columns unwritten #6598

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ca30b5a
[FlyDSL] [MoE] Fix stage-1 grid leaving padded intermediate columns u…
micah-wil Oct 15, 2026
2d263b6
[FlyDSL] [MoE] Read the stage-1 XCD swizzle's grid from the launch
micah-wil Oct 19, 2026
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31 changes: 18 additions & 13 deletions aiter/ops/flydsl/kernels/mixed_moe_gemm_2stage_common.py
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Original file line number Diff line number Diff line change
Expand Up @@ -430,6 +430,20 @@ def x_lds_elem():
fp4_ratio = 2 if a_dtype == "fp4" else 1
gui_ratio = 1 if gate_up_interleave else 2

# Stage 1 writes the intermediate's unpadded columns rounded up to stage 2's
# K tile (tile_k // 2): stage 2 reads that far, and columns left unwritten
# are stale memory (NaN through mfma_scale even against zero weights). The
# grid skips the rest of the padding, counted in w1 rows: two per column,
# (gate, up), in both the separated and the interleaved layouts.
inter_dim_written = inter_dim - inter_dim_pad
if not gate_only:
tile_k_stage2 = tile_k // 2
inter_dim_written = min(
inter_dim,
-(-inter_dim_written // tile_k_stage2) * tile_k_stage2,
)
n_rows_skipped = 2 * (inter_dim - inter_dim_written)

if True:

def _emit_moe_gemm1(
Expand Down Expand Up @@ -522,7 +536,7 @@ def _emit_moe_gemm1(
num_xcds = 8
one = arith.constant(1, index=True)
tile_n_idx = arith.constant(tile_n, index=True)
inter_pad_idx = arith.constant(2 * inter_dim_pad, index=True)
inter_pad_idx = arith.constant(n_rows_skipped, index=True)
if const_expr(mock_gate_only or gate_up_interleave):
grid_x = (n_in - inter_pad_idx + tile_n_idx - one) // tile_n_idx
else:
Expand Down Expand Up @@ -2952,23 +2966,14 @@ def _launch_mixed_moe_gemm1(
# manual finalize is needed.
ctx = CompilationContext.get_current()

inter_dim_pad_total = arith.constant(2 * inter_dim_pad, index=True)
tile2_pad = 0
if const_expr(not gate_only):
tile_k_stage2 = tile_k // 2
tile2_pad = (
tile_k_stage2 - (inter_dim - inter_dim_pad) % tile_k_stage2
) % tile_k_stage2

n_rows_skipped_idx = arith.constant(n_rows_skipped, index=True)
inter_in = fx.Index(i32_inter_in)
tile_n_index = arith.constant(tile_n, index=True)
if const_expr(mock_gate_only or gate_up_interleave):
gx = (
inter_in - inter_dim_pad_total + tile2_pad + tile_n_index - 1
) // tile_n_index
gx = (inter_in - n_rows_skipped_idx + tile_n_index - 1) // tile_n_index

@jamesETsmith jamesETsmith Oct 16, 2026

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Maybe I'm missing something, but doesn't this gx recompute the grid_x we compute above in line 541? If it does, I think we should consolidate the vars and if not, would it be worth enforcing that they're the same with a check/comparison?

@micah-wil micah-wil Oct 19, 2026

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Yep I think you are right, will clean that up as part of this PR

else:
gx = (
(inter_in - inter_dim_pad_total + tile2_pad + 2 * tile_n_index - 1)
(inter_in - n_rows_skipped_idx + 2 * tile_n_index - 1)
// tile_n_index
// arith.constant(2, index=True)
)
Expand Down
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