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[HIP] [FlyDSL] add mxfp8 w_scale 1*32 (scalea/b nonpreshuffle) - #6407

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valarLip merged 4 commits into
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mxfp8_nonshuffle
Oct 14, 2026
Merged

valarLip merged 4 commits into
mainfrom
mxfp8_nonshuffle

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Motivation

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@solinzby1
solinzby1 requested review from a team and amd-ruitang3 and a balanced review from Copilot October 12, 2026 03:15
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🏷️ CI Guide

Runs automatically on every PR:

  • ✅ Pre-checks (submodule verification, code formatting)
  • ✅ Aiter op tests (gfx942 + gfx950)
  • ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label Tests
ci:gfx1250-ffm-triton Run the five-shard gfx1250 FFM Triton test suite
ci:triton-300x Run an additional Triton test job on MI300X in PRs (added automatically when gfx942 configs change); main branch always runs both MI35X and MI300X
ci:triton-355 Run the full Triton test suite on MI35X, not only the tests the change affects
ci:multi-gpu Aiter multi-GPU tests on the 8-GPU runner
ci:sglang SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm vLLM benchmark: DeepSeek-V4-Pro, MiniMax-M3-MXFP4
ci:all All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
Add labels via the sidebar or gh pr edit 6407 --add-label <label>

One backend per PR:
A PR changes one kernel backend: [Triton/Gluon] (Triton and Gluon count as one), [HIP], [ASM], [CK], [OPUS] or [FlyDSL]. If the title ends up with two backend tags, split the PR -- as stacked pull requests when one part cannot merge without the other.

PR title tags & labels:
Component tags ([Triton/Gluon], [HIP], [CK], [ASM], ...) are added to the PR title and as PR labels automatically from the changed files and re-synced on every push — change-type tags like [fix]/[Perf], op tags like [MLA], and human labels (ci:*) are left untouched. Add the no-auto-title label to stop the title rewrites; labels stay in sync either way.

@github-actions github-actions Bot changed the title add mxfp8 w_scale 1*32 (scalea/b nonpreshuffle) [HIP] [FlyDSL] add mxfp8 w_scale 1*32 (scalea/b nonpreshuffle) Oct 12, 2026
@solinzby1
solinzby1 requested a review from aoli26 October 12, 2026 03:16

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🔵 Needs a closer look

The low-level GPU and AOT changes have unresolved findings and no supplied hardware validation results.

3 open findings
What changed in this PR

Adds gfx950 support for MXFP8 GEMM using unshuffled row-major 1×32 scales.

Changes:

  • Adds FlyDSL row-scale loading and dispatch.
  • Adds gfx950 tuning configurations and tuner.
  • Extends tests and AOT compilation support.
File Description
op_tests/​test_gemm_a8w8_mxfp8_bpreshuffle.py Extends correctness testing to gfx950.
csrc/​gemm_a8w8_mxfp8_bpreshuffle/​gemm_a8w8_mxfp8_bpreshuffle_tune.py Adds the gfx950 tuner.
aiter/​ops/​gemm_op_a8w8.py Dispatches gfx950 to FlyDSL.
aiter/​ops/​flydsl/​mxscale_preshuffle_kernels.py Adds row-scale host dispatch.
aiter/​ops/​flydsl/​kernels/​gemm/​mxscale_preshuffle.py Implements LDS-staged row-scale loading.
aiter/​ops/​flydsl/​gemm_tune/​flydsl_gemm_mxscale_preshuffle_common.py Adds scale-layout-aware candidate filtering.
aiter/​ops/​flydsl/​gemm_a8w8_mxfp8.py Adds architecture-aware GEMM routing.
aiter/​configs/​model_configs/​dsv4_a8w8_mxfp8_bpreshuffle_tuned_gemm.csv Adds gfx950 tuned rows.
aiter/​aot/​flydsl/​gemm.py Adds AOT support for row-scale specializations.

🧠 Review effort: Balanced


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Comment thread aiter/aot/flydsl/gemm.py
batched_skipped = set()
# The mxfp8 1x32 table's gfx950 rows name mxpsh kernels that read the
# unshuffled per-1x32 scales; every other table's mxpsh rows are blockscale.
mxfp8_table = "a8w8_mxfp8_bpreshuffle" in os.path.basename(csv_path)
f"1x32 scales (needs K%128==0 and N a multiple of a tile_n)"
)
kernel_name = ki.name
_warn_untuned(M, N, K, "fp8", "fp8", kernel_name)
Copilot AI balanced review requested due to automatic review settings October 13, 2026 09:54

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🟡 Changes recommended

Cross-XCD cache coherence, retained large workspaces, and gfx950 availability reporting need correction.

6 open findings

🧠 Review effort: Balanced

M,
N,
num_tiles,
torch.float32 if fused_f32 else torch.bfloat16,
Comment thread aiter/ops/gemm_op_a8w8.py Outdated
Comment on lines +2254 to +2255
gfx950 rows are FlyDSL mxpsh kernels (unshuffled 1x32 scales); an untuned
gfx950 shape runs the mxpsh heuristic tile.
Copilot AI balanced review requested due to automatic review settings October 13, 2026 16:59

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Comment on lines +143 to +145
dgroup0=Vec.from_elements(
[fx.Int32(pred), g0[1], g0[2], g0[3]], fx.Int32
).ir_value(),
Comment thread aiter/ops/gemm_op_a8w8.py
w_scale: Tensor,
dtype: torch.dtype = dtypes.bf16,
out: Tensor | None = None,
a_scale_preshuffled: bool = False,
gfx1250,256,256,7168,16384,flydsl,44,4,19.036,flydsl_mxfp8_32_bpreshuffle_compute_wmma_t128x256x128_mw2_nw2_nb3_sk4_cm4_cn4,3158.73,6782.20,0.0
gfx1250,256,512,7168,16384,flydsl,38,2,27.797,flydsl_mxfp8_32_bpreshuffle_compute_wmma_t128x256x128_mw2_nw2_nb3_sk2_cm4_cn2_fsk,4326.39,4932.30,0.0
gfx1250,256,1024,7168,16384,flydsl,-1,1,48.453,flydsl_mxfp8_32_bpreshuffle_compute_wmma_t128x256x128_mw2_nw2_nb3_sk1_cm4_cn4,4963.99,3159.63,0.0
gfx1250,256,2048,7168,16384,flydsl,-1,1,87.731,flydsl_mxfp8_32_bpreshuffle_compute_wmma_t256x256x128_mw2_nw2_nb2_sk1_cm4_cn4,5483.06,2109.55,0.0
Copilot AI balanced review requested due to automatic review settings October 14, 2026 03:39

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