[Config] config: GLM-5.3-Flash fused shared MoE rows for gfx942

[jin-amd]

Why

GLM-5.3-Flash shared-expert fusion changes the routed fused-MoE dispatch from E=288, topk=8 to E=289, topk=9. The ninth expert is always selected with weight 1.0, so one AITER launch runs the routed and shared experts together. The vLLM side is vllm-project/vllm#59221.

The gfx942 TP-local signatures are:

• TP2: model/intermediate (4096,1024), E=289, topk=9
• TP4: model/intermediate (4096,512), E=289, topk=9
• TP8: model/intermediate (4096,256), E=289, topk=9

The existing model-config set covers this dispatch only on gfx950 (#5735). On gfx942 every signature uses fallback kernels, up to 2.1x slower than the rows below.

What this adds

Fifteen gfx942/cu304 rows in a dedicated GLM-5.3 fused-shared table, all one-stage 64x256 with block_m 64:

• TP2, TP4 and TP8: M={1024,2048,4096,8192,16384}

The matching untuned table records the complete 15-shape power-of-two ladder for each TP (45 source rows). These are the same buckets as #5500, the routed (E=288, topk=8) counterpart on gfx942; the dispatch keys are disjoint.

All three signatures were tuned with the standard fused-MoE tuner over the ASM block-FP8 family. Only rows improving AITER's production operator by at least 3% were retained; the other thirty buckets keep fallback dispatch. Two of them are worth noting:

• TP8 M=1: the fallback returned wrong output until [CK] [Bugfix] Keep two K tiles per split in blockscale MoE stage-1 split-K #5979 (a CK stage-1 split-K bug), which is in this branch's base. With the fix it is correct and faster than the best tuned candidate (34.9 versus 59.8 µs).
• TP2 M=2: the best candidate gained only 3.3% and 4.8% in the two verification runs, about 3 µs. [Config] configs: GLM-5.3-Flash a8w8 blockscale fused-MoE configs for gfx942 #5500 dropped the same shape at 2.1-2.9%, so it stays on the fallback here too.

Validation

• All 15 retained rows have err1=0.0%, run_1stage=1, kernelName2 empty, and us2=0.
• Production-operator execution passed for every retained row, in both runs.
• Speedup over the fallback at M=1024/2048/4096/8192/16384, mean of two runs:
  • TP2: 1.21x / 1.57x / 1.53x / 1.21x / 1.09x
  • TP4: 1.14x / 1.55x / 1.91x / 1.79x / 1.43x
  • TP8: 1.18x / 1.38x / 1.82x / 2.14x / 1.70x
• Direct fused-versus-separate comparison through the production fused_moe (separate: the routed call plus the shared expert alone) at TP2, TP4 and TP8, from M=2 through M=16384: all outputs finite, minimum cosine 0.999867, maximum mean absolute error 8.99e-3 against mean absolute outputs of 0.27-0.64.
• test_csv_validation.py and test_config_shape_collision.py: 39 passed, 48 subtests passed. All 15 rows survive the AITER_CONFIG_FMOE_FILE merge.
• No new dispatch key occurs in any other fused-MoE table on main (only [Config] configs: GLM-5.3 fused shared MoE rows for gfx950 #5735's gfx950 rows share the shapes), or in the open PRs that add fused-MoE rows ([CK] [FlyDSL] [CI] [Bugfix] Explicit gfx in shipped fused-MoE tuning CSVs #5315, [Config] configs: GLM-5.3-Flash a8w8 blockscale fused-MoE configs for gfx942 #5500, [Config] [DSv4] Tuned decode moe kernels for mori-EP backend- #41119 #5821, [Config] [Perf] Retune GLM5 MXFP4 FMoE for gfx950 #5902, [Config] Add tuned a8w4 fused-MoE configs for DeepSeek V4.1-Flash (TP4 + EP, gfx950) #5904).
• Like every gfx942 path for this model, these kernels do not apply GLM-5.3's swiglu_limit=10. With w1 scaled so the clamp changes a third of the gate/up values, this table, the two-stage fallback and the one-stage fallback for the unfused shape all match the unclamped fp32 reference (cosine 0.9990-0.9991), not the clamped one (0.84-0.87). Fixing that needs clamp support in the gfx942 kernels, separate from this table.

Hardware: MI325X (gfx942, 304 CUs).
Image: amdsiloai/vllm:vllm-openai-rocm-glm5.3-flash-mi325-28092026-pr57161; the TP2 M=2 and swiglu_limit re-checks ran in an image built on it.
Tuning branch base: upstream ROCm/aiter main at 475cf0f60. The branch is now on a1455f1c4, whose fused-MoE changes do not touch these rows.

Submission Checklist

• Looked over the ROCm contributing guidelines.
• Targeting the repository default branch (main).
• Included successful config-validation and production-operator results.
• Commit includes the required DCO sign-off.
• CI green for the updated head.

[github-actions]

🏷️ CI Guide

Runs automatically on every PR:

• ✅ Pre-checks (submodule verification, code formatting)
• ✅ Aiter op tests (gfx942 + gfx950)
• ✅ Triton tests on MI35X (only when aiter/ops/triton/** or related paths are changed)

Extended tests (opt-in via labels):

Label	Tests
ci:gfx1250-ffm-triton	Run the five-shard gfx1250 FFM Triton test suite
ci:triton-300x	Run an additional Triton test job on MI300X in PRs; main branch always runs both MI35X and MI300X
multigpu	Aiter multi-GPU tests on the 8-GPU runner
ci:sglang	SGLang integration tests: DeepSeek-R1-MXFP4 accuracy, Qwen 3.5 accuracy
ci:atom	ATOM benchmark: DeepSeek-R1-0528, GPT-OSS-120B
ci:atom_full	ATOM accuracy suite for PR and main models from ATOM models_accuracy.json
ci:vllm	vLLM benchmark: GPT-OSS-120B, DeepSeek-R1-0528, Kimi-K2.5
ci:all	All standard extended tests (excludes ci:atom_full)

Only add ci:atom_full for FlyDSL or Triton upgrades.
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[Copilot]

Copilot review overview

🟡 Changes recommended

The selected one-stage ASM path does not receive the model’s required swiglu_limit=10, so clamped-SiLU semantics are not preserved.

Review effort: Balanced
Findings: 1

Open (1)

• One-stage ASM path ignores GLM-5.3 swiglu_limit · New

What changed in this PR

Adds gfx942 fused shared-expert MoE configurations for GLM-5.3-Flash.

Changes:

• Adds 17 tuned TP2/TP4/TP8 dispatch rows.
• Adds the complete 45-shape tuning input ladder.

File	Description
a8w8_blockscale_untuned_fmoe_glm5_3_flash_shared_gfx942.csv	Defines tuning shapes.
a8w8_blockscale_tuned_fmoe_glm5_3_flash_shared_gfx942.csv	Adds selected gfx942 kernels.

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[Copilot]

Copilot review overview

🟡 Changes recommended

The missing TP8 M=1 tuned row leaves the reported incorrect fallback active.

Review effort: Balanced
Findings: 1

Open (1)

• Add missing TP8 M=1 configuration row · New

Resolved since last review (1)

• One-stage ASM path ignores GLM-5.3 swiglu_limit

[Copilot]

Copilot review overview

🟡 Changes recommended

The PR description documents an unrelated split-K code fix and provides no applicable validation for these configuration rows.

Review effort: Balanced
Findings: 1

Open (1)

• PR description does not match GLM-5.3 tuning table changes · New

Resolved since last review (1)

• Add missing TP8 M=1 configuration row

[Copilot]

Copilot review overview

🔵 Needs a closer look

The description documents an unrelated split-K implementation rather than the configuration changes and their validation.

Review effort: Balanced
Findings: 1

Open (1)

• PR description does not match GLM-5.3 tuning table changes

[samremes]

lgtm