[HIP] Add FP4 output mode to indexer_qk_rope_quant_and_cache - #5484
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The fused indexer op only emitted FP8, so callers wanting the FP4 paged MQA-logits kernels had to skip the fusion and write the FP4 index cache themselves. Supplying q_scale_out and kv_cache_scale now switches the op to the packed e2m1 + e8m0 layout that flydsl_pa_mqa_logits_fp4 and its prefill variant read directly. FP4 mode keeps the weight unscaled: that kernel applies the per-group Q scale inside the MFMA and takes weights_scale as its own fp32 scalar, so folding either one here would be wrong and would round through bf16. Omitting the two scale buffers leaves the FP8 contract byte for byte.
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The fused indexer op only emitted FP8, so callers wanting the FP4 paged MQA-logits kernels had to skip the fusion and write the FP4 index cache themselves. Supplying q_scale_out and kv_cache_scale now switches the op to the packed e2m1 + e8m0 layout that flydsl_pa_mqa_logits_fp4 and its prefill variant read directly. FP4 mode keeps the weight unscaled: that kernel applies the per-group Q scale inside the MFMA and takes weights_scale as its own fp32 scalar, so folding either one here would be wrong and would round through bf16. Omitting the two scale buffers leaves the FP8 contract byte for byte. Signed-off-by: Xiake Sun <xiake.sun@amd.com>
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Extends
indexer_qk_rope_quant_and_cachewith an FP4 output mode, so a DSA sparse indexer can keep its keys as packed E2M1 plus e8m0 scales and haveflydsl_pa_mqa_logits_fp4(and its prefill variant) score them straight out of the paged cache. Before this, that op only emitted FP8, so a caller wanting the FP4 scorers had to skip the fusion and write the FP4 index cache itself.API
FP4 mode is selected by supplying both new optional trailing arguments. Omitting them leaves the FP8 contract untouched.
weights_outcarries the plain weight under FP4, with neitherq_scalenorweights_scalefolded in. The FP8 path foldsq_scalebecause its per-(token, head) scale has nowhere else to go; under FP4 the MFMA consumes the per-group e8m0 scale directly, so folding is impossible, andweights_scaleis left out because the scorer applies its own fp32 scalar while folding it here would round through bf16.Anything outside
head_dim=128,rope_dim=64,group_size=32,kv_block_size=64,n_heads % 16 == 0is rejected on the host with a specific message.Verification
compute_all_q_ropexis_neox), zero mismatching bytes across all five outputs. Heads=32 exercises theqs_padzero-padding path, heads=64 the unpadded one.scale_fmtvalues, bothpreshufflevalues, bothis_neox, bothcompute_all_q_rope, and three token counts.flydsl_pa_mqa_logits_fp4at GLM-5.2 shapes (H=32, D=128, kv_block=64, block_k=256) gives cosine 1.000000 and top-64 overlap 1.00 for next_n 1 and 4, max abs error 1.5e-8. Against independent bf16 ground truth the same pipeline scores cosine 0.980, the expected FP4 quantization loss.One deliberate deviation
The
argminoracle inop_tests/test_flydsl_pa_mqa_logits_fp4.pycannot be byte-reproduced by any AMD FP4 kernel: measured against the hardwarev_cvt_scalef32_pk_fp4_f32converter over 524,288 random bf16 values it differs on 5.87% of nibbles (27,774 are+0vs-0, identical after dequant; 2,989 are exact midpoints whereargminrounds toward -inf and the hardware rounds half-to-even). AITER's ownf32_to_mxfp4matches the hardware on all 524,288. This implements the hardware semantics, matching_rope_rotate_activation_fp4quant,rmsnorm_rope_rotate_activation_fp4quant_kvcacheandper_1x32_f4_quant_hip, so it emits-0codes where that oracle produces+0.Follow-up
The preshuffle offset arithmetic now exists in both
cache_kernels.cuanddsv4_rotate_quant.cuunder distinct names. That ABI-critical math living in two translation units is a drift hazard; a shared header would be the right cleanup.The consumer side is ROCm/ATOM#perf-sparse-indexer-fp4, which depends on this branch.