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[FlyDSL] [MegaMoE] A4W4 mega_moe operator - #4980
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… from 25 commits for rebase onto main; originals in backup-pre-rebase-20261010_111557) Co-authored-by: Cursor <cursoragent@cursor.com>
…ry + fix epr52/56 fp4 prelude + drop tuning scaffolding
Refactor
- Replace _apply_a4_tuning with a NetworkProfile registry keyed by the full
(experts_per_rank, model_dim, inter_dim) identity. _match_network() resolves
the network; imperative per-network tuners _tune_r1 / _tune_v4_pro /
_tune_kimi_k3 plus a shared _TuningContext. Quant gating is via
ctx.apply_fp4 / ctx.a_dtype (R1/V4-Pro tune FP4 only, Kimi-K3 both dtypes).
Identity-based dispatch (networks that only share an experts-per-rank)
- epr32 is shared by R1 (7168x2048) and GLM-5.2 (6144x2048). Keying tuning on
the full shape identity means GLM-5.2 no longer inherits R1's FP4 table, its
prelude, or the epr32 bucket-8192 base rule; it falls back to the base config
(plus the dtype-generic FP4 SBM64 async-copy rule) until tuned in its own
right. EPLB family profiles (epr 52/56 at V4's shape) get the prelude but no
tuner. Accuracy verified on 8 GPUs: GLM-5.2 a4w4 relL2~0.206 across bs 8..512
(rtol 0.25); a8w4 is byte-identical to main's base.
epr 52/56 fix
- The fp4 common prelude is a pre-rule applied to every matched non-K3 network,
so the EPLB redundant-expert profiles epr 52/56 (which have no tuner) keep it.
Scaffolding cleanup
- Remove the _env_tune_hook (*_TUNE_JSON / *_TUNE_BUCKETS) sweep injection and
the R1_A8W4_TRY_A4 experiment toggle; simplify apply_fp4 to a_dtype == FP4.
- Drop the now-orphaned `import os` (not imported on main) and two unused
_TuningContext fields.
Minimize diff vs main
- Revert .github/scripts/aiter_test.sh: the added test_mega_moe_v2.py case was
unreachable (the file stays in skip_tests, checked before the case).
- Revert op_tests/multigpu_tests/bench_mega_moe_v2.py: the Mori-comparison
rewrite was unrelated to a4w4; restore main's online-faithful benchmark.
- Drop the zipf routing mode from test_mega_moe_v2.py (_make_inputs matches main).
Verified byte-identical production config: full matrix epr {32,48,112} fp4+fp8
(294 pts) and EPLB epr {48,52,56} (294 pts) both 0 mismatches vs pre-change
baseline. black --check and ruff pass.
Co-authored-by: Cursor <cursoragent@cursor.com>
…xed-slot FP4 SBM) P1: payload_chunk_rows is part of the dispatch wire protocol (senders chunk by it, receivers predict publisher counts by it), so it must be identical across every token bucket in a MAX-MTPR class or uneven-rank prefill deadlocks Stage1's equality wait. The per-bucket overrides (16384/32768 -> 1536, rest 384) are replaced by a single class-wide base of 1536 in _select_large_stage1. Measured rank-invariant and a no-op on buckets 2048/4096/8192 while recovering ~14% e2e at bucket 16384 and ~8% at 32768 vs the 384 base. P2: the FP4 SBM->64 promotion (bucket<=128) is skipped for fixed-slot dispatch. Fixed-slot receive capacity ll_cap=ceil(8*mtpr/32)*32 is 32 at mtpr 1/2/4, which is not divisible by 64, so the promotion crashed Stage1's 'fuse_cap % tile_m == 0' compile assert on all ranks. Fixed-slot now keeps the legal SBM32 FP4 geometry. Validated: CPU invariants P1=0/P2=0 violations; full config diff = 28 expected keys only (K3/GLM/other dtypes unchanged); GPU graph_replay=PASS across R1 large buckets, v4_pro a4w4 tiny mtpr, and K3 a8w4 smoke. Co-authored-by: Cursor <cursoragent@cursor.com>
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…nge) Co-authored-by: Cursor <cursoragent@cursor.com>
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Conflict in aiter/aot/flydsl/mega_moe.py: #4980 added A4W4 MegaMoE and taught the old script its kernels (quant mode, FP4 output and scale shapes). The replay needs none of that, since MegaMoEV2 picks them itself; it only adds "a4w4" to DEFAULT_QUANTS, which takes the default build from 96 jobs to 192. The A4W4 replay passes all 96 jobs. Every one of the 3218 artifacts the old script builds for A4W4 is in its cache: 3082 byte-identical, 136 differing only in v_add3_u32 vs v_add_u32 + v_sub_u32 (2-7 asm lines), the FlyDSL/LLVM run-to-run variation also seen for A8W4. The other 144 are the mask_topk_ids=True combine kernels the old script never built. Signed-off-by: zhimding <zhimding@amd.com>
2 tasks done
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Motivation
Extend MegaMoE to support the DeepSeek V4 Pro A4W4 path alongside A8W4, while reducing Stage2 cross-rank traffic and latency with blockwise FP8 P2P scatter.
Technical Details
fp8_blockwise_1x32Stage2 transport:Test Plan
Hardware: Single-node 8× AMD MI355X (gfx950).
Software: PyTorch 2.9.1 + ROCm 7.2, FlyDSL 0.3.1, Mori 1.1.2.dev32.
Model: DeepSeek-V4-Pro (Quark MXFP4, H=7168, I=3072, 384 routed experts, topk=6, 61 layers).
Serving: TP8, DP-attention, Expert Parallel,
max-model-len=9472,max-num-batched-tokens=8192,max-num-seqs=512, FP8 KV cache, block 16, prefix cache off. EPLB interval/window 200, balancedness threshold 2.0.Workload: ISL/OSL 8192/1024, range ratio 1.0, ignore EOS, seed 0, inf rate, 64 warmup requests.
EPLB: r0 = 0 redundant (naive, util 0.85); r64 = 64 redundant (biased, util 0.90).
MegaMoE: MTPR 8192, Stage2 P2P
fp8_blockwise_1x32.Prompts: c512 = 5120, c4096 = 8192.
Test Result
After fixing the hang issue, MegaMoE exhibits some performance regression in small batch size scenarios. The performance data has been updated with the measurements obtained after the fix.
r0, Concurrency 512
r0, Concurrency 4096
r64, Concurrency 512
r64, Concurrency 4096
Summary: MegaMoE A4W4 vs Standard Mori A8W4 (FP8 dispatch)
Summary: MegaMoE A4W4 vs Mori A4W4 — same quant, DeepSeek-R1 (sglang)
Isolates the backend (both sides A4W4, so the delta is purely MegaMoE fused
megakernel vs Standard Mori dispatch — unlike the V4-Pro table above, which mixes
quant and backend). Same sglang (PR#35619 branch) and same aiter for both runs;
DeepSeek-R1-MXFP4, EPLB r0, concurrency 512, inf rate. Both: 2048/2048 completed,
0 errors. Reported on two routing workloads:
random(ISL/OSL 8192/1024,prefill-heavy) and
sharegpt(real-traffic prompt/routing distribution,decode-heavy).
Note (data correction): an earlier revision of this table reported Mori A4W4
at 36,654 tok/s (→ +33.6%). That figure came from a non-quant-aligned Mori run;
re-running Mori under the same A4W4 dispatch, same machine, and same
aiter/sglang build yields 45,723.99 tok/s, so the true same-quant backend gap on
randomis +3.5% (not +33.6%). All numbers above are the corrected, quant-aligned measurements.random (ISL/OSL 8192/1024, prefill-heavy)
sharegpt (real routing, decode-heavy)
At the same A4W4 quant (so the delta is purely backend), MegaMoE's fused megakernel
with P2P all-to-all overlap wins on both workloads. On the real-traffic
sharegptrouting it delivers +12.4% total throughput with ~11% lower TTFT and TPOT.
On the prefill-heavy
randomworkload (ISL=8192, dispatch-bandwidth bound) the gapnarrows to +3.5% total throughput with ~6% lower TPOT; here Mori's TTFT is
marginally lower, since the long-prefill phase is dominated by dispatch bandwidth
rather than kernel fusion. The fusion/overlap benefit is largest in the
decode-bound regime that dominates real serving traffic.
End-to-end accuracy (GSM8K, DeepSeek-R1-MXFP4, same A4W4)
Full end-to-end serving accuracy on GSM8K (not just the operator relL2 gate),
measured on the same aligned A4W4 runs, Invalid 0.000 for all:
MegaMoE A4W4 matches Mori on
random(0.965 = 0.965) and is within noise onsharegpt(0.975 vs 0.950), confirming the fused A4W4 backend is accuracy-neutralend-to-end — consistent with the operator-level gate (A4W4 relL2 < 0.28).
Accuracy (GSM8K, DeepSeek-V4-Pro)
All backends pass the operator-level accuracy gate (A4W4 relL2 < 0.25, A8W4 relL2 < 0.10)
Test Result
MegaMoE A4W4 delivers +2.4% to +5.5% total throughput over MegaMoE A8W4 across the four DeepSeek-V4-Pro serving configurations (r0/c512 +5.5%, r0/c4096 +4.2%, r64/c512 +2.4%, r64/c4096 +5.4%), by halving the weight and activation bandwidth. Accuracy is preserved (GSM8K full 0.9530 vs 0.9522, both PASS).
Submission Checklist