[GFX950] Relocate MLA Gluon kernel and unify decode dispatch - #4450
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Extended tests (opt-in via labels):
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This now overlaps #4405's caller-owned |
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@JohnQinAMD Thanks for pointing this out. I added equivalent split-policy and boundary coverage in commit dd521e2. I confirmed that the #4450 measurements were collected on this machine, which has 8× AMD Instinct MI355X GPUs ( The new coverage includes:
Focused unit-test result: Explicit split-boundary command: python op_tests/test_mla.py --decode-only -c 1 31 32 63 64 65 8192 -b 1 -n 12,1 -d bf16 -kvd bf16 -k 512 -qn 512 -qr 64 -vh 512 -blk 1 --varlen -splits 32All seven boundary cases passed the PyTorch golden check with I also reran the automatic graph-safe policy without an explicit override at contexts 4K, 100K, and 262K. Output and LSE checks passed at all three lengths, and the varlen This should preserve #4405's focused split-policy and boundary coverage while keeping #4450 as the single runtime scheduling implementation. |
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The optimization from this PR has been incorporated into #4555, so I’m drafting this PR. |
Add aiter_mla_gluon.py and extend aiter_backend.py to route fp8 decode through aiter mla_gluon with batch>1, zero-pad/repeat head padding for h12, and graph-capture-safe kv_scale / min_kv_seq_len. Update cache_ops.py and forward_mla.py for aiter/aiter/fp8 prefill: cache_ops matches sgl-project#33341; forward_mla adds bf16 Q when kv_cache_dtype is fp8 (Gluon bh16bn128 requires bf16 Q). aiter runtime dependencies (container/image, not in this repo): - ROCm/aiter#4480 (required): fp8 Gluon bh16bn128, batch>1, 64-bit KV base. - ROCm/aiter#4450 (required for decode CUDA graph): graph-safe KV splits and HIP stream setup in mla_gluon. - Triton >= 3.7 for Gluon cga_layout on gfx950. sgl-project#33341: this change set vendors overlapping prefill/KV hunks (cache_ops identical; aiter_backend prefill zero-pad refactored and extended for fp8 Gluon). Does not require sgl-project#33341 to merge first; rebase onto sgl-project#33341 when landed to drop duplicate cache_ops diff. Co-authored-by: Cursor <cursoragent@cursor.com>
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Move the current gfx950 kernel into the architecture-specific hierarchy and connect validated low-head BF16 workloads to the unified MLA entry. Signed-off-by: LiuYinfeng01 <yinfeliu@amd.com>
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Add aiter_mla_gluon.py and extend aiter_backend.py to route fp8 decode through aiter mla_gluon with batch>1, zero-pad/repeat head padding for h12, and graph-capture-safe kv_scale / min_kv_seq_len. Update cache_ops.py and forward_mla.py for aiter/aiter/fp8 prefill: cache_ops matches sgl-project#33341; forward_mla adds bf16 Q when kv_cache_dtype is fp8 (Gluon bh16bn128 requires bf16 Q). aiter runtime dependencies (container/image, not in this repo): - ROCm/aiter#4480 (required): fp8 Gluon bh16bn128, batch>1, 64-bit KV base. - ROCm/aiter#4450 (required for decode CUDA graph): graph-safe KV splits and HIP stream setup in mla_gluon. - Triton >= 3.7 for Gluon cga_layout on gfx950. sgl-project#33341: this change set vendors overlapping prefill/KV hunks (cache_ops identical; aiter_backend prefill zero-pad refactored and extended for fp8 Gluon). Does not require sgl-project#33341 to merge first; rebase onto sgl-project#33341 when landed to drop duplicate cache_ops diff. Co-authored-by: Cursor <cursoragent@cursor.com>
Summary
Scope
The split-scheduling performance optimization originally developed in this PR has already landed through #4555. This revision does not add a new split policy or further kernel performance tuning.
The moved kernel is byte-for-byte identical to the current file on main, so the relocation carries the implementation from #4555 and the subsequent NaN fix from #4711 without reimplementing either change.
Unified decode dispatch
The gfx950 Gluon path is selected only for the validated configuration:
Unsupported configurations continue to use the existing Triton path.
Validation