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fa0763b
[PERF] MXFP4 (a4w4) MoE backend for gfx950 (#3470)
ColorsWind Jun 15, 2026
b035559
rename aux dir to moe_aux
Bernard-Liu Jun 17, 2026
46ecc44
Port flydsl a4w4 MoE onto randomflow_pr (coexist with HIP #3470) (#3788)
fsx950223 Jun 18, 2026
0a0d0ef
flydsl mxfp4 gemm1/gemm2: raw-pointer (data_ptr i64) ABI
ColorsWind Jun 21, 2026
6cbec45
flydsl mxfp4 gemm2: large-M (BM128) optimizations
ColorsWind Jun 21, 2026
b51ec85
flydsl mxfp4 gemm1: hardware exp2 in silu
ColorsWind Jun 21, 2026
b242ba6
[RadeonFlow] flydsl mxfp4 a4w4 MoE: bring gemm1/gemm2 to parity with …
ColorsWind Jun 22, 2026
05567f6
[RadeonFlow] Integrate HIP Sort/Quant in MoE Pipeline (#3827)
ftyghome Jun 22, 2026
a595f9e
lgkmcnt
benenzhu Jun 22, 2026
e90d47f
flydsl mxfp4 gemm2: pipeline fp4-out epilog LDS reads (lgkmcnt -68%, …
benenzhu Jun 22, 2026
ead7f82
Merge branch 'main' of github.com:ROCm/aiter into dev/randomflow_pr
benenzhu Jun 22, 2026
4fd9bca
mxfp4 moe: route Kimi rows to FlyDSL port + replace kernelName regex …
benenzhu Jun 22, 2026
ef6046a
mxfp4 moe: drop HIP gemm1/gemm2 backend, run gemm exclusively on FlyD…
benenzhu Jun 22, 2026
a389c89
Merge pull request #1 from RadeonFlow/radeonflow_pr_flydsl_perf2
ColorsWind Jun 22, 2026
48ac23b
flydsl mxfp4 gemm1: prologue vmcnt relax + BM128 scale-first ds_read
ColorsWind Jun 22, 2026
35d2a30
flydsl mxfp4 gemm2: float fabs/maxnum amax in mxfp4out epilog
ColorsWind Jun 22, 2026
6376142
flydsl mxfp4 moe: gate gemm2 mxfp4-out solely on AITER_MXFP4_INTERMED…
ColorsWind Jun 22, 2026
da4cb4c
Merge dev/randomflow_pr into radeonflow_pr_flydsl_perf (resolve #3861…
ftyghome Jun 22, 2026
d2d28f0
[RadeonFlow] flydsl mxfp4 a4w4 MoE: improv perf (#3861)
ColorsWind Jun 23, 2026
6a50c71
mxfp4 moe tuner: enumerate the FlyDSL a4w4 port as tuning candidates
benenzhu Jun 23, 2026
5a163cb
Merge remote-tracking branch 'rocm/dev/randomflow_pr' into dev/random…
benenzhu Jun 23, 2026
2fafb5c
mxfp4 moe: fix ruff lint (unused imports/var + lambda-assignment)
benenzhu Jun 23, 2026
38195a0
mxfp4 moe: apply black formatting
benenzhu Jun 23, 2026
f3c44b3
mxfp4 moe aux: guard gfx950-only fp4-cvt builtin for multi-arch builds
benenzhu Jun 23, 2026
0ac4ffd
mxfp4 moe: drop dead HIP-era tests + the unused D_INTER=192 shape
benenzhu Jun 23, 2026
9eb354c
mxfp4 moe: add more shape dispatch
ftyghome Jun 23, 2026
91c4336
mxfp4 moe: split model dispatch csv files
ftyghome Jun 23, 2026
6a580ab
mxfp4 moe: fix a4w4 test weight layout (use a16w4 shuffle for the port)
benenzhu Jun 23, 2026
318ae1e
mxfp4 moe configs: normalize guitlv CSV line endings to LF
benenzhu Jun 23, 2026
b8520c2
mxfp4 moe: drop test_mxfp4_moe_128k_chunk.py (gfx950-only, fails on M…
benenzhu Jun 23, 2026
2f33c0f
Merge branch 'main' into dev/randomflow_pr
coderfeli Jun 23, 2026
5fd3ceb
flydsl mxfp4 gemm1: compiler-managed K-loop fence
ftyghome Jun 23, 2026
dac7d97
flydsl mxfp4 gemm2: compiler-managed barrier, drop hand-tuned waitcnts
ftyghome Jun 23, 2026
c708799
Merge upstream/dev/randomflow_pr into radeonflow_pr_flydsl_perf
ftyghome Jun 23, 2026
8814138
mxfp4 moe: drop orphan gemm_common.hpp; revert jit lineinfo flag
ColorsWind Jun 23, 2026
499b4e9
[RadeonFlow] accu fix + clean (#3884)
ColorsWind Jun 24, 2026
437bcf9
chore: merge guitlv csv into fp4 csv
ftyghome Jun 23, 2026
e333923
cleanup: remove unnecessary comments
ftyghome Jun 24, 2026
66ea2c3
sort rewrite
benenzhu Jun 24, 2026
ff7b819
fix: mxfp4 tuned config lock to manually selected ones (#3887)
ftyghome Jun 24, 2026
c13225c
feat(mxfp4-moe): AOT pre-compile + flyc.compile low-overhead launch f…
coderfeli Jun 24, 2026
9cfa7dd
fix(mxfp4-moe): import fused_moe deps from source modules for AOT
benenzhu Jun 24, 2026
aff0ca3
fix(mxfp4-moe): extract pure kname parsing to avoid JIT load during AOT
benenzhu Jun 24, 2026
7bcee9b
fix(mxfp4-moe): make FlyDSL AOT precompile GPU-free
benenzhu Jun 24, 2026
515d90d
fix: add missing dsv4 shapes
ftyghome Jun 24, 2026
c50c3e3
Merge remote-tracking branch 'origin/dev/randomflow_pr' into radeonfl…
ftyghome Jun 24, 2026
d82bb7c
rename kernels and csv to align original style
coderfeli Jun 24, 2026
e54baa4
style: black-format mxfp4_kname (wrap long ValueError)
coderfeli Jun 24, 2026
71f5314
fix aot
zhangnju Jun 24, 2026
8ce2969
Merge remote-tracking branch 'rocm/main' into dev/randomflow_pr2
benenzhu Jun 24, 2026
d99e500
revert non-kimik2_5 fp4 fmoe CSVs to rocm/main
benenzhu Jun 24, 2026
36efe5b
feat(mxfp4-moe): enable the mxmoe a4w4 pipeline only for interleave g…
coderfeli Jun 24, 2026
22d8988
suport seperate
coderfeli Jun 24, 2026
c931100
mxfp4 moe: e8m0 scale rounding Even -> RoundUp
ColorsWind Jun 24, 2026
169eee8
flydsl mxfp4 gemm1/gemm2: size A_q/A_scale buffer resources from runt…
ColorsWind Jun 24, 2026
b576566
mxfp4 moe test: pin test_moe_2stage to Kimi-K2.5 TP4 a4w4
ColorsWind Jun 24, 2026
2d07af8
Merge upstream/dev/randomflow_pr into radeonflow_pr_flydsl_perf
ftyghome Jun 24, 2026
6d25aea
[RadeonFlow] max_m / round_up fix (#3904)
ColorsWind Jun 25, 2026
68d493f
align shuffle scale
coderfeli Jun 25, 2026
eb385ab
Merge remote-tracking branch 'rocm/main' into dev/randomflow_pr2
benenzhu Jun 25, 2026
dcfe1b2
format
benenzhu Jun 25, 2026
0ae49ae
flydsl mxfp4 gemm1/gemm2: remove dead MAX_M buffer-size code
ftyghome Jun 25, 2026
266255d
flydsl mxfp4 gemm1/gemm2: move module globals into instantiation params
ftyghome Jun 25, 2026
e7209f3
flydsl mxfp4 gemm1/gemm2: strip comments and docstrings
ftyghome Jun 25, 2026
ab78e7c
flydsl mxfp4 gemm: extract shared helpers into mxfp4_gemm_common
ftyghome Jun 25, 2026
22fc814
flydsl mxfp4 gemm1: use DPP for epilog amax cross-lane reduction
ftyghome Jun 25, 2026
51a8c89
flydsl mxfp4 gemm2: disable post-misched for BM16 decode kernel
ftyghome Jun 25, 2026
b032808
Merge upstream/dev/randomflow_pr into radeonflow_pr_flydsl_perf
ftyghome Jun 25, 2026
f55b133
refactor: moe sorting
ftyghome Jun 25, 2026
af5366e
Merge remote-tracking branch 'origin/radeonflow_pr_flydsl_perf' into …
ftyghome Jun 25, 2026
ee083f9
Merge remote-tracking branch 'origin/dev/randomflow_pr' into radeonfl…
ftyghome Jun 25, 2026
64fcc96
format
benenzhu Jun 25, 2026
fbd2a2a
refactor: drop gate_moe in csv dispatch
ftyghome Jun 26, 2026
ff1fa90
Merge pull request #3952 from RadeonFlow/dev/randomflow_pr
Bernard-Liu Jun 26, 2026
94d0b26
Merge remote-tracking branch 'origin/main' into pr3832_resolve
coderfeli Jun 27, 2026
49fa6d1
revert: fused_moe act change
ftyghome Jun 27, 2026
53a8b23
revert: Kimi K2.5 additional tests
ftyghome Jun 27, 2026
d26c1c9
revert: dispatch sorting impl only by emit_aux
ftyghome Jun 27, 2026
9b396ed
feat: standalone mxfp4 flydsl tuner
ftyghome Jun 27, 2026
d8a837f
Merge pull request #3968 from RadeonFlow/dev/randomflow_pr
Bernard-Liu Jun 28, 2026
7631599
format
benenzhu Jun 28, 2026
086689f
chore: add BM64 kernel (#3975)
ftyghome Jun 29, 2026
fa55390
[RadeonFlow] avoid scatter reduce copy + addXCD swizzle support (#3978)
ColorsWind Jun 29, 2026
78f8eee
fix: handle empty kernelName and AOT-cover CK-Tile split-K epilogue
benenzhu Jun 29, 2026
7d15e55
fix: round silu_and_mul_fq VEC to power of two, cap at 8
benenzhu Jun 29, 2026
c685033
fix aot
Bernard-Liu Jun 29, 2026
efc3686
Merge remote-tracking branch 'rocm/main' into dev/randomflow_pr7
benenzhu Jun 29, 2026
e7599aa
fix comment for sort_backend
Bernard-Liu Jun 30, 2026
104b512
Merge remote-tracking branch 'origin/dev/randomflow_pr' into dev/rand…
Bernard-Liu Jun 30, 2026
03eb921
Merge branch 'main' into dev/randomflow_pr
coderfeli Jun 30, 2026
f22b61b
fix(test): correct a4w4 weight layout and gate mode in moe_2stage
ColorsWind Jun 30, 2026
2098023
fix(mxfp4): default interleave=False for a4w4 gemm1
ColorsWind Jun 30, 2026
f6a94d9
feat(mxfp4): add Kimi-K2.5 TP=2 (E=385, inter=1024) aux instance
ColorsWind Jun 30, 2026
55c09eb
Merge remote-tracking branch 'rocm/dev/randomflow_pr' into fix/mxfp4-…
benenzhu Jul 1, 2026
c295b0d
format
benenzhu Jul 1, 2026
c457b2e
Merge remote-tracking branch 'rocm/main' into fix/mxfp4-a4w4-separate…
benenzhu Jul 1, 2026
9790753
[flydsl] gemm2 a4w4: give epilog lds_acc its own LDS, drop leading ba…
ColorsWind Jul 1, 2026
884eacd
[mxfp4_moe] aux cleanup: drop dead sort_scales D_INTER, add scatter s…
ColorsWind Jul 1, 2026
52eea17
add more dsv4 shapes
Bernard-Liu Jun 30, 2026
5adcf05
mxmoe support mp&timeout
Bernard-Liu Jul 1, 2026
6732142
fix layout bug
Bernard-Liu Jul 2, 2026
9209b51
add expert_mask assert
Bernard-Liu Jul 2, 2026
dfb43d2
style: format gemm_moe_tune.py with black
Bernard-Liu Jul 3, 2026
e3b4b07
Merge branch 'main' into dev/randomflow_pr
Bernard-Liu Jul 3, 2026
c0619e9
simplify annotations
Bernard-Liu Jul 3, 2026
46dd1d5
docs: annotate epilogue AOT compile-only stream/swiglu_limit args
benenzhu Jul 6, 2026
16dec44
Merge remote-tracking branch 'rocm/main' into fix_moe
benenzhu Jul 6, 2026
238d4ec
fix ci
benenzhu Jul 6, 2026
3d0b31e
Merge remote-tracking branch 'rocm/main' into fix_moe
benenzhu Jul 7, 2026
aa65f59
Merge remote-tracking branch 'rocm/main' into fix_moe
benenzhu Jul 8, 2026
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1 change: 1 addition & 0 deletions aiter/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,7 @@ def getLogger():
from .ops.moe_op import * # noqa: F403,E402
from .ops.moe_sorting import * # noqa: F403,E402
from .ops.moe_sorting_opus import * # noqa: F403,E402
from .ops.moe_mxfp4_aux import * # noqa: F403,E402
from .ops.pa_sparse_prefill_opus import * # noqa: F403,E402
from .ops.pos_encoding import * # noqa: F403,E402
from .ops.cache import * # noqa: F403,E402
Expand Down
5 changes: 5 additions & 0 deletions aiter/aot/flydsl/common.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ class OpKind(enum.Enum):
construction errors instead of silently routing to the wrong code path."""

MOE = "moe"
MXFP4_MOE = "mxfp4_moe"
GEMM = "gemm"
GROUPED_MOE = "grouped_moe"
CHUNK_GDN_H = "chunk_gdn_h"
Expand Down Expand Up @@ -136,6 +137,8 @@ def _collect_aot_jobs_for(kind: OpKind) -> list[dict[str, Any]]:
parent process, just shifted once out of every child."""
if kind is OpKind.MOE:
from .moe import DEFAULT_CSVS, parse_csv
elif kind is OpKind.MXFP4_MOE:
from .mxfp4_moe import DEFAULT_CSVS, parse_csv
elif kind is OpKind.GEMM:
from .gemm import DEFAULT_CSVS, parse_csv
elif kind is OpKind.GROUPED_MOE:
Expand All @@ -150,6 +153,8 @@ def _collect_aot_jobs_for(kind: OpKind) -> list[dict[str, Any]]:
def _compile_one_config_for(kind: OpKind) -> Callable[..., dict[str, Any]]:
if kind is OpKind.MOE:
from .moe import compile_one_config
elif kind is OpKind.MXFP4_MOE:
from .mxfp4_moe import compile_one_config
elif kind is OpKind.GEMM:
from .gemm import compile_one_config
elif kind is OpKind.GROUPED_MOE:
Expand Down
140 changes: 121 additions & 19 deletions aiter/aot/flydsl/moe.py
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,29 @@ def parse_csv(csv_path: str):
)
stage1_out_dtype = stage1_params.get("out_dtype") if stage1_params else None

# cktile_ stage1 runs a FlyDSL post-activation epilogue (silu ->
# silu_and_mul_fq, swiglu -> swiglu_and_mul) that the flydsl_-only loop
# below skips, so emit its job here. The cache key needs only
# (inter_dim, topk)/(inter_dim), which the CSV shape covers regardless
# of runtime split_k.
if stage1_name.startswith("cktile_"):

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still consider ck?

@benenzhu benenzhu Jul 7, 2026

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aiter.moe_cktile_2stages_gemm1(...)
if split_k>1 & interleaved:
flydsl_silu_and_mul_interleaved(...)

It's a ck-tile moe but will run to a FlyDSL reduce kernel.
Added this so that the Cl can passed (which require all FlyDSL kernels must be AOT ones).

epi_job = {
"kernel_name": f"cktile_epilogue_{act}",
"stage": "epilogue",
"act": act,
"inter_dim": inter_dim,
"topk": topk,
"cu_num": cu_num,
# Not used by the epilogue compile; zeroed so dedup keys on
# (act, inter_dim, topk, cu_num) only.
"model_dim": 0,
"experts": 0,
}
key = job_identity(epi_job)
if key not in seen:
seen.add(key)
jobs.append(epi_job)

for col in ("kernelName1", "kernelName2"):
name = row.get(col, "").strip()
if not name or not name.startswith("flydsl_"):
Expand Down Expand Up @@ -748,6 +771,69 @@ def _make_a_user(a_dtype_user_shape):
)


def _precompile_epilogue_to_cache(act: str, inter_dim: int, topk: int):
"""Precompile the CK-Tile split-K post-activation epilogue kernel.

cktile_moe_stage1 with split_k>1 emits a workspace of interleaved gate/up
output and then runs a FlyDSL epilogue to apply the activation:
silu -> flydsl_silu_and_mul_interleaved (silu_and_mul_fq with
quant_mode="none", gui_layout=True)
swiglu -> flydsl_swiglu_and_mul_interleaved (swiglu_and_mul)
Dispatch through the same runtime builders so the cache key matches; the
key depends only on inter_dim (swiglu) / (inter_dim, topk) (silu), and the
row/token dims are dynamic, so dummy buffers suffice.
"""
import torch

from aiter.ops.flydsl.moe_kernels import (
_get_compiled_silu_fused,
_get_compiled_swiglu,
_run_compiled,
)

dev = torch.device("cpu")
rows = 256

# COMPILE_ONLY=1 makes the executor compile + persist the artifact without
# launching the kernel; without it _run_compiled would dispatch on the
# (absent) GPU under fake tensors and fault.
with compile_only_env():
if act == "swiglu":
exe = _get_compiled_swiglu(inter_dim)
x = torch.zeros((rows, inter_dim * 2), dtype=torch.bfloat16, device=dev)
out = torch.zeros((rows, inter_dim), dtype=torch.bfloat16, device=dev)
# trailing 0 = stream: null/default (compile-only, never launched)
_run_compiled(exe, (x, out, rows, 0))
return

exe = _get_compiled_silu_fused(
inter_dim, topk, quant_mode="none", gui_layout=True, act="silu"
)
x = torch.zeros((rows, inter_dim * 2), dtype=torch.bfloat16, device=dev)
out = torch.zeros((rows, inter_dim), dtype=torch.bfloat16, device=dev)
empty_scale = torch.empty(0, dtype=torch.uint8, device=dev)
empty_i32 = torch.empty(0, dtype=torch.int32, device=dev)
empty_f32 = torch.empty(0, dtype=torch.float32, device=dev)
sorted_token_ids = torch.zeros(rows, dtype=torch.int32, device=dev)
num_valid_ids = torch.zeros(2, dtype=torch.int32, device=dev)
_run_compiled(
exe,
(
_ptr_view_safe(x),
_ptr_view_safe(out),
_ptr_view_safe(empty_scale),
_ptr_view_safe(sorted_token_ids),
_ptr_view_safe(num_valid_ids),
_ptr_view_safe(empty_i32),
_ptr_view_safe(empty_f32),
rows,
sorted_token_ids.shape[0],
float("inf"), # swiglu_limit (unused for silu)
0, # stream: null/default (compile-only, kernel is never launched)
),
)


def compile_one_config(
kernel_name: str,
model_dim: int,
Expand All @@ -765,10 +851,15 @@ def compile_one_config(
Returns a dict with timing info.
"""
aot_arch = cu_num_to_arch(cu_num, default=MOE_AOT_ARCH_DEFAULT)
is_epilogue = kwargs.get("stage") == "epilogue"
shape_str = (
f"{kernel_name} "
f"model_dim={model_dim} inter_dim={inter_dim} "
f"E={experts} topk={topk}"
f"{kernel_name} inter_dim={inter_dim} topk={topk}"
if is_epilogue
else (
f"{kernel_name} "
f"model_dim={model_dim} inter_dim={inter_dim} "
f"E={experts} topk={topk}"
)
)
result = {
"kernel_name": kernel_name,
Expand All @@ -785,14 +876,21 @@ def compile_one_config(
override_env("FLYDSL_GPU_ARCH", aot_arch),
FakeTensorMode(),
):
_precompile_to_cache(
model_dim=model_dim,
inter_dim=inter_dim,
experts=experts,
topk=topk,
cu_num=cu_num,
**kwargs,
)
if is_epilogue:
_precompile_epilogue_to_cache(
act=kwargs.get("act", "silu"),
inter_dim=inter_dim,
topk=topk,
)
else:
_precompile_to_cache(
model_dim=model_dim,
inter_dim=inter_dim,
experts=experts,
topk=topk,
cu_num=cu_num,
**kwargs,
)
elapsed = time.time() - t0
result["compile_time"] = elapsed
print(f" [OK] compile {elapsed:6.1f}s {shape_str} arch={aot_arch}")
Expand Down Expand Up @@ -831,26 +929,30 @@ def main():

stage1_jobs = [j for j in all_jobs if j["stage"] == 1]
stage2_jobs = [j for j in all_jobs if j["stage"] == 2]
epilogue_jobs = [j for j in all_jobs if j["stage"] == "epilogue"]
print("=" * 72)
print("FlyDSL MoE AOT Pre-compilation")
print("=" * 72)
for csv_path in csv_paths:
print(f" CSV: {csv_path}")
print(f" Stage1 jobs: {len(stage1_jobs)}")
print(f" Stage2 jobs: {len(stage2_jobs)}")
print(f" Total jobs: {len(all_jobs)}")
print(f" Stage1 jobs: {len(stage1_jobs)}")
print(f" Stage2 jobs: {len(stage2_jobs)}")
print(f" Epilogue jobs: {len(epilogue_jobs)}")
print(f" Total jobs: {len(all_jobs)}")
print(" Compile arch: (from cu_num)")
print(f" Cache dir: {cache_dir}")
print(f" Target arch: {arch}")
print("=" * 72)

total_t0 = time.time()

# Stage1 and stage2 kernels are independent compiles (each writes its
# own artifact to cache; stage2 does not read stage1's output), so they
# share a single pool for maximum fan-out instead of two serial passes.
print(f"\n--- Compiling {len(all_jobs)} kernels (stage1 + stage2) ---")
results = run_jobs_parallel(compile_one_config, stage1_jobs + stage2_jobs)
# Stage1, stage2 and CK-Tile epilogue kernels are independent compiles
# (each writes its own artifact to cache; none reads another's output), so
# they share a single pool for maximum fan-out instead of serial passes.
print(f"\n--- Compiling {len(all_jobs)} kernels (stage1 + stage2 + epilogue) ---")
results = run_jobs_parallel(
compile_one_config, stage1_jobs + stage2_jobs + epilogue_jobs
)

total_elapsed = time.time() - total_t0

Expand Down
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