Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

cpu/stm32{f0,g0,c0}: fix ADC initialization sequence #21230

Open
wants to merge 2 commits into
base: master
Choose a base branch
from

Conversation

crasbe
Copy link
Contributor

@crasbe crasbe commented Feb 19, 2025

Contribution description

Most of the issue was described in #21222.
tl;dr: The initialization sequence was not entirely correct and at least for the STM32C0, changing the resolution did not work.

I rewrote the calibration and initialization sequence to follow the guides outlined in the reference manuals more closely.
It should be noted here that the reference manuals involve more steps and checks the newer the devices gets. The sequence for the F0 is very simple [1], for the G0 more complicated [2] and quite involved for the C0 [3].

Currently I don't have a STM32G0 nucleo, so the changes are untested for that family. Soon(ish) I'll buy one though.

Tested with:

Testing procedure

I recommend to apply #21223 as well to check all resolutions at once. The updated test is now in master and I rebased this PR.
For some STM32C0xx boards, PR #20939 has to be applied with my proposed changes as well if you want to use the NUCLEO-C071 (not really convenient). The NUCLEO-C031 is supported by master already.

You can simply use the adc test BOARD=nucleo-f030r8 make flash term.

Before this PR with the STM32C071RB (Pin A0 connected to 3.3V, all samples have the same resolution):

main(): This is RIOT! (Version: 2024.10-devel-351-gbf1684-stm32c0-additions)

RIOT ADC peripheral driver test

This test will sample all available ADC lines once every 100ms with
6 to 16-bit resolution and print the sampled results to STDOUT.
Not all MCUs support all resolutions, unsupported resolutions
are printed as -1.

Successfully initialized ADC_LINE(0)
Successfully initialized ADC_LINE(1)
Successfully initialized ADC_LINE(2)
Successfully initialized ADC_LINE(3)
Successfully initialized ADC_LINE(4)
Successfully initialized ADC_LINE(5)
ADC_LINE(0): 1680 4095 4095 4094    -1    -1
ADC_LINE(1): 1563 1161  958  859    -1    -1
ADC_LINE(2): 1125 1016  959  937    -1    -1
ADC_LINE(3): 1032 970  934  919    -1    -1
ADC_LINE(4): 1024 962  928  914    -1    -1
ADC_LINE(5): 1082 1026 1005  985    -1    -1

ADC_LINE(0): 4095 4095 4095 4095    -1    -1
ADC_LINE(1): 1345 1038  905  840    -1    -1
ADC_LINE(2): 923 921  923  924    -1    -1
ADC_LINE(3): 885 900  907  908    -1    -1
ADC_LINE(4): 954 925  912  907    -1    -1
ADC_LINE(5): 961 967  969  972    -1    -1

ADC_LINE(0): 4095 4095 4095 4095    -1    -1
ADC_LINE(1): 1373 1051  909  842    -1    -1
ADC_LINE(2): 971 941  931  926    -1    -1
ADC_LINE(3): 920 913  912  911    -1    -1
ADC_LINE(4): 963 927  914  909    -1    -1
ADC_LINE(5): 956 967  969  971    -1    -1

With this PR on STM32F030R8 and STM32C071RB (Pin A3 connected to +3.3V, samples have different resolution):

ADC_LINE(0): 31 1òmain(): This is RIOT! (Version: 2024.04-devel-2100-gc6897-pr/stm32f0g0c0_adc)

RIOT ADC peripheral driver test

This test will sample all available ADC lines once every 100ms with
6 to 16-bit resolution and print the sampled results to STDOUT.
Not all MCUs support all resolutions, unsupported resolutions
are printed as -1.

Successfully initialized ADC_LINE(0)
Successfully initialized ADC_LINE(1)
Successfully initialized ADC_LINE(2)
Successfully initialized ADC_LINE(3)
Successfully initialized ADC_LINE(4)
Successfully initialized ADC_LINE(5)
ADC_LINE(0): 14  80  383 1688    -1    -1
ADC_LINE(1): 30 118  473 1887    -1    -1
ADC_LINE(2): 17  83  369 1593    -1    -1
ADC_LINE(3): 63 255 1023 4095    -1    -1
ADC_LINE(4): 37 134  509 1961    -1    -1
ADC_LINE(5): 31 121  477 1913    -1    -1

ADC_LINE(0): 30 119  474 1896    -1    -1
ADC_LINE(1): 32 122  481 1902    -1    -1
ADC_LINE(2): 17  82  367 1580    -1    -1
ADC_LINE(3): 63 255 1023 4095    -1    -1
ADC_LINE(4): 36 134  506 1951    -1    -1
ADC_LINE(5): 31 121  474 1911    -1    -1

ADC_LINE(0): 31 122  478 1907    -1    -1
ADC_LINE(1): 32 123  482 1912    -1    -1
ADC_LINE(2): 17  81  364 1579    -1    -1
ADC_LINE(3): 63 255 1023 4095    -1    -1
ADC_LINE(4): 36 133  507 1951    -1    -1
ADC_LINE(5): 31 122  479 1908    -1    -1

Issues/PRs references

Fixes #21222.

[1] https://www.st.com/resource/en/reference_manual/rm0360-stm32f030x4x6x8xc-and-stm32f070x6xb-advanced-armbased-32bit-mcus-stmicroelectronics.pdf p. 185 section 12.3.2 and 12.3.3
[2] https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf p. 278 section 14.3.3 and 14.3.4
[3] https://www.st.com/resource/en/reference_manual/rm0490-stm32c0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf p. 290 section 16.4.3 and section 16.4.4

@github-actions github-actions bot added Platform: ARM Platform: This PR/issue effects ARM-based platforms Area: cpu Area: CPU/MCU ports labels Feb 19, 2025
@crasbe crasbe force-pushed the pr/stm32f0g0c0_adc branch from c6897e0 to 6ba243d Compare February 20, 2025 10:33
@benpicco benpicco added the CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR label Feb 21, 2025
@riot-ci
Copy link

riot-ci commented Feb 21, 2025

Murdock results

✔️ PASSED

e1ac185 fixup! cpu/stm32{f0,g0,c0}: fix ADC initialization sequence

Success Failures Total Runtime
10271 0 10271 09m:31s

Artifacts

@crasbe
Copy link
Contributor Author

crasbe commented Feb 21, 2025

I applied some ideas from the STM32WL PR to this one, namingly giving _disable_adc a return value as well and skipping the initialization if the ADC already has been initialized.

Tested again with the nucleo-f030r8 and nucleo-c071rb boards.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Area: cpu Area: CPU/MCU ports CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: ARM Platform: This PR/issue effects ARM-based platforms
Projects
None yet
Development

Successfully merging this pull request may close these issues.

cpu/stm32{f0, g0, c0}: Fix ADC
3 participants