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cpu/riscv_common/periph_timer: Fix timer_clear() #19112

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merged 1 commit into from
Jan 9, 2023
Merged

cpu/riscv_common/periph_timer: Fix timer_clear() #19112

merged 1 commit into from
Jan 9, 2023

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maribu
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@maribu maribu commented Jan 8, 2023

Contribution description

Previously, timer_clear() was a no-op, resulting in spurious IRQs from already canceled timeouts. This fixes the issue.

Testing procedure

$ make BOARD=hifive1b flash test -C tests/periph_timer
[...]
Welcome to pyterm!
Bench Clock Reset Complete

ATE0-->ATE0
OK
AT+BLEINIT=0-->OK
AT+CWMODE=0-->OK

Help: Press s to start test, r to print it is ready
READY
s
START
main(): This is RIOT! (Version: 2023.01-devel-773-g441b69)

Test for peripheral TIMERs

Available timers: 1

Testing TIMER_0:
TIMER_0: initialization successful
TIMER_0: stopped
TIMER_0: set channel 0 to 5000
TIMER_0: starting
TIMER_0: channel 0 fired at SW count  3164199 - init:  3164199

TEST SUCCEEDED

(In master, the test fails with a spurious IRQ.)

Issues/PRs references

#18976

@maribu
cpu/riscv_common/periph_timer: Fix timer_clear()
525751c 
Previously, timer_clear() was a no-op, resulting in spurious IRQs from
already canceled timeouts. This fixes the issue.
@maribu maribu added Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors) CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Area: cpu Area: CPU/MCU ports labels Jan 8, 2023
@maribu maribu requested review from aabadie and kaspar030 January 8, 2023 23:15
@github-actions github-actions bot added the Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms label Jan 8, 2023
@maribu maribu mentioned this pull request Jan 8, 2023
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benpicco
benpicco approved these changes Jan 8, 2023
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bors merge

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bors bot commented Jan 8, 2023

🕐 Waiting for PR status (GitHub check) to be set, probably by CI. Bors will automatically try to run when all required PR statuses are set.

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bors bot commented Jan 8, 2023

GitHub status checks took too long to complete, so bors is giving up. You can adjust bors configuration to have it wait longer if you like.

@benpicco benpicco added CI: high priority If set, builds of this PR will be queued before others CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR and removed CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Jan 9, 2023
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riot-ci commented Jan 9, 2023

Murdock results

✔️ PASSED

525751c cpu/riscv_common/periph_timer: Fix timer_clear()

Success Failures Total Runtime
6770 0 6770 12m:58s

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maribu commented Jan 9, 2023

bors retry

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bors bot commented Jan 9, 2023

Build succeeded:

@bors bors bot merged commit ecf0ad3 into RIOT-OS:master Jan 9, 2023
@maribu maribu deleted the cpu/riscv_common/periph/coretimer.c branch January 9, 2023 10:00
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maribu commented Jan 9, 2023

Thx :)

@aabadie aabadie mentioned this pull request Jan 9, 2023
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@benpicco benpicco benpicco approved these changes

@aabadie aabadie Awaiting requested review from aabadie

@kaspar030 kaspar030 Awaiting requested review from kaspar030

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Area: cpu Area: CPU/MCU ports CI: high priority If set, builds of this PR will be queued before others CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms Type: bug The issue reports a bug / The PR fixes a bug (including spelling errors)
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@maribu @riot-ci @benpicco