fixup! location of second CC register in 8/16 bit mode

all other registers start at the same location regardless of mode.

cpu/sam0_common/periph/timer.c

@@ -42,6 +42,16 @@ static inline TcCount32 *dev(tim_t tim)
     return &timer_config[tim].dev->COUNT32;
 }
 
+static inline TcCount16 *dev16(tim_t tim)
+{
+    return &timer_config[tim].dev->COUNT16;
+}
+
+static inline TcCount8 *dev8(tim_t tim)
+{
+    return &timer_config[tim].dev->COUNT8;
+}
+
 static inline void wait_synchronization(tim_t tim)
 {
 #if defined(TC_SYNCBUSY_MASK)
@@ -115,6 +125,24 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
     return 0;
 }
 
+static void _set_cc(tim_t tim, int cc, unsigned int value)
+{
+    const uint16_t flags = timer_config[tim].flags;
+
+    if (flags & TC_CTRLA_MODE_COUNT32) {
+        dev(tim)->CC[cc].reg = value;
+        return;
+    }
+
+    if (flags & TC_CTRLA_MODE_COUNT8) {
+        dev8(tim)->CC[cc].reg = value;
+        return;
+    }
+
+    /* 16 bit is the default */
+    dev16(tim)->CC[cc].reg = value;
+}
+
 int timer_set_absolute(tim_t tim, int channel, unsigned int value)
 {
     DEBUG("Setting timer %i channel %i to %i\n", tim, channel, value);
@@ -123,12 +151,12 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
     switch (channel) {
     case 0:
         dev(tim)->INTFLAG.reg = TC_INTFLAG_MC0;
-        dev(tim)->CC[0].reg = value;
+        _set_cc(tim, 0, value);
         dev(tim)->INTENSET.bit.MC0 = 1;
         break;
     case 1:
         dev(tim)->INTFLAG.reg = TC_INTFLAG_MC1;
-        dev(tim)->CC[1].reg = value;
+        _set_cc(tim, 1, value);
         dev(tim)->INTENSET.bit.MC1 = 1;
         break;
     default: