Merge pull request #10883 from gschorcht/esp_common_xtensa

cpu/esp*: Xtensa vendor code moved to esp_common

cpu/esp32/Makefile.include

@@ -73,6 +73,7 @@ USEMODULE += random
 USEMODULE += stdio_uart
 USEMODULE += xtensa
 
+INCLUDES += -I$(RIOTCPU)/esp_common/vendor/
 INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/
 INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/esp-idf/include
 INCLUDES += -I$(RIOTCPU)/$(CPU)/vendor/esp-idf/include/esp32
@@ -88,7 +89,6 @@ INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/include
 INCLUDES += -I$(RIOTBOARD)/common/$(CPU)/include
 INCLUDES += -I$(RIOTCPU)/$(CPU)
 
-CFLAGS  += -DRIOT_OS
 CFLAGS  += -DSCHED_PRIO_LEVELS=32
 CFLAGS  += -DSDK_NOT_USED -DCONFIG_FREERTOS_UNICORE=1 -DESP_PLATFORM
 CFLAGS  += -DLOG_TAG_IN_BRACKETS

cpu/esp32/include/irq_arch.h

@@ -37,65 +37,54 @@ extern "C" {
 extern volatile uint32_t irq_interrupt_nesting;
 
 /**
-  * @brief fixed allocated CPU interrupt numbers that are used by RIOT
-  * @{
-  */
-#define CPU_INUM_GPIO       2   /* level interrupt, low priority = 1 */
-#define CPU_INUM_CAN        3   /* level interrupt, low priority = 1 */
-#define CPU_INUM_UART       5   /* level interrupt, low priority = 1 */
-#define CPU_INUM_RTC        9   /* level interrupt, low priority = 1 */
-#define CPU_INUM_I2C        12  /* level interrupt, low priority = 1 */
-#define CPU_INUM_WDT        13  /* level interrupt, low priority = 1 */
-#define CPU_INUM_SOFTWARE   17  /* level interrupt, low priority = 1 */
-#define CPU_INUM_ETH        18  /* level interrupt, low priority = 1 */
-#define CPU_INUM_TIMER      19  /* level interrupt, medium priority = 2 */
+ * @name   CPU interrupt numbers
+ *
+ * All interrupts that are used for RIOT-OS are preallocated and fix.
+ * The allocated interrupts are all level interrupts, most of them with
+ * low priority.
+ *
+ * @{
+ */
+#define CPU_INUM_GPIO       2   /**< Level interrupt with low priority 1 */
+#define CPU_INUM_CAN        3   /**< Level interrupt with low priority 1 */
+#define CPU_INUM_UART       5   /**< Level interrupt with low priority 1 */
+#define CPU_INUM_RTC        9   /**< Level interrupt with low priority 1 */
+#define CPU_INUM_I2C        12  /**< Level interrupt with low priority 1 */
+#define CPU_INUM_WDT        13  /**< Level interrupt with low priority 1 */
+#define CPU_INUM_SOFTWARE   17  /**< Level interrupt with low priority 1 */
+#define CPU_INUM_ETH        18  /**< Level interrupt with low priority 1 */
+#define CPU_INUM_TIMER      19  /**< Level interrupt with medium priority 2 */
 /** @} */
 
-#if defined(SDK_INT_HANDLING) || defined(DOXYGEN)
 /**
- * @brief   Macros that have to be used on entry into and reset from an ISR
+ * @name   Macros to enter and exit an ISR
+ *
+ * Since all the stuff is done in `_frxt_int_enter` and `_frxt_int_exit`, these
+ * macros are doing nothing and are kept only for source code compatibility.
  *
- * NOTE: since they use a local variable they can be used only in same function
  * @{
  */
-/** Macro that has to be used at the entry point of an ISR */
-#define irq_isr_enter()    int _irq_state = irq_disable (); \
-                           irq_interrupt_nesting++;
-
-/** Macro that has to be used at the exit point of an ISR */
-#define irq_isr_exit()     if (irq_interrupt_nesting) \
-                               irq_interrupt_nesting--; \
-                           irq_restore (_irq_state); \
-                           if (sched_context_switch_request) \
-                               thread_yield();
-
-#else /* SDK_INT_HANDLING */
-
-/* in non SDK task handling all the stuff is done in _frxt_int_enter and _frxt_int_exit */
-#define irq_isr_enter() /* int _irq_state = irq_disable (); \
-                           irq_interrupt_nesting++; */
-
-#define irq_isr_exit()  /* if (irq_interrupt_nesting) \
-                               irq_interrupt_nesting--; \
-                           irq_restore (_irq_state); */
-
-#endif /* SDK_INT_HANDLING */
+#define irq_isr_enter()
+#define irq_isr_exit()
+/** @} */
 
 /**
- * @brief   Macros to enter and exit from critical region
+ * @name   Macros to enter and exit a critical region
+ *
+ * @note: since they use a local variable they can be used only in same function
  *
- * NOTE: since they use a local variable they can be used only in same function
  * @{
  */
-#define critical_enter()   int _irq_state = irq_disable ()
+#define critical_enter()   int _irq_state = irq_disable()
 #define critical_exit()    irq_restore(_irq_state)
+/** @} */
 
 /**
- * @brief   Macros to enter and exit from critical region with state variable
+ * @name   Macros to enter and exit a critical region with state variable
+ * @{
  */
-#define critical_enter_var(m)   m = irq_disable ()
+#define critical_enter_var(m)   m = irq_disable()
 #define critical_exit_var(m)    irq_restore(m)
-
 /** @} */
 
 #ifdef __cplusplus

cpu/esp32/include/xtensa_conf.h

@@ -27,11 +27,7 @@ extern "C" {
  * @brief   Xtensa ASM code specific default stack sizes
  * @{
  */
-#if defined(SDK_INT_HANDLING)
-#define ISR_STACKSIZE                 (8)
-#else
 #define ISR_STACKSIZE                 (2048)
-#endif
 /** @} */
 
 #ifdef __cplusplus

cpu/esp32/thread_arch.c

@@ -131,12 +131,12 @@ char* thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_sta
     uint8_t *top_of_stack;
     uint8_t *sp;
 
-    top_of_stack = (uint8_t*)((uint32_t)stack_start + stack_size-1);
+    top_of_stack = (uint8_t*)((uint32_t)stack_start + stack_size - 1);
 
     /* BEGIN - code from FreeRTOS port for Xtensa from Cadence */
 
     /* Create interrupt stack frame aligned to 16 byte boundary */
-    sp = (uint8_t*)(((uint32_t)(top_of_stack+1) - XT_STK_FRMSZ - XT_CP_SIZE) & ~0xf);
+    sp = (uint8_t*)(((uint32_t)(top_of_stack + 1) - XT_STK_FRMSZ - XT_CP_SIZE) & ~0xf);
 
     /* Clear whole stack with a known value to assist debugging */
     #if !defined(DEVELHELP) && !defined(SCHED_TEST_STACK)
@@ -183,7 +183,7 @@ char* thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_sta
 
     uint32_t *p;
 
-    p = (uint32_t *)(((uint32_t) top_of_stack+1 - XT_CP_SIZE));
+    p = (uint32_t *)(((uint32_t)(top_of_stack + 1) - XT_CP_SIZE) & ~0xf);
     p[0] = 0;
     p[1] = 0;
     p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;

cpu/esp32/vendor/Makefile

@@ -1,5 +1,4 @@
 # Add a list of subdirectories, that should also be built:
 DIRS += esp-idf
-DIRS += xtensa
 
 include $(RIOTBASE)/Makefile.base

cpu/esp32/vendor/README.md

@@ -7,6 +7,3 @@ The files that are part of [esp-open-rtos](https://github.com/SuperHouse/esp-ope
 ### esp-idf
 
 The files in this directory and all subdirectories are from the Espressif IoT Development Framework[ESP-IDF](https://github.com/espressif/esp-idf.git), the official development framework for ESP32. All of these files are copyright of Espressif Systems (Shanghai) PTE LTD or their respective owners and licensed under the Apache License, Version 2.0. Please refer the copyright notice in these files for details.
-
-### xtensa
-The files in this directory are from the [FreeRTOS port for Xtensa](https://github.com/tensilica/freertos) configurable processors and Diamond processors. All of these files are copyright of Cadence Design Systems Inc. and licensed under the MIT license.

cpu/esp32/vendor/esp-idf/esp32/dport_access.c

@@ -19,9 +19,9 @@
  * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt.
  */
 
-#ifdef RIOT_OS
+#ifdef RIOT_VERSION
 #include "esp_common.h"
-#endif /* RIOT_OS */
+#endif /* RIOT_VERSION */
 
 #include <stdint.h>
 #include <string.h>