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  • Saint Petersburg State University of Telecommunications
  • Saint Petersburg, Russia

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  1. verilog-transceiver Public

    Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

    Verilog 3 2

  2. axis-i2c-master Public

    AXI-Stream I2C Master module

    SystemVerilog 2

  3. fpga-useful-list Public

    List of useful materials on FPGA topic

    3

  4. axis-uart Public

    AXI-Stream UART module

    SystemVerilog 1

  5. FPGA-Tools-Docker Public

    Docker Container with Iverilog, Yosys, Verilator, Verible, Gowin Education and more.

    Dockerfile 2

  6. axis-spi Public

    AXI-Stream SPI modules

    SystemVerilog

1,160 contributions in the last year

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Contribution activity

April 2025

Opened 2 issues in 1 repository
RDSik/axis-spi 2 open
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