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Saint Petersburg State University of Telecommunications
- Saint Petersburg, Russia
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verilog-transceiver
verilog-transceiver PublicEducational project for the Xilinx ZedBoard Zynq-7000 Development Kit
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FPGA-Tools-Docker
FPGA-Tools-Docker PublicDocker Container with Iverilog, Yosys, Verilator, Verible, Gowin Education and more.
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1,160 contributions in the last year
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Contribution activity
April 2025
Created 79 commits in 4 repositories
Opened 2 issues in 1 repository
RDSik/axis-spi
2
open
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Incorrect slave axis tready signal work in spi slave
This contribution was made on Apr 19
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Incorrect spi slave work in SPI_MODE = 2
This contribution was made on Apr 19