Skip to content
View Princyjf's full-sized avatar
1 follower · 0 following

Achievements

Achievement: Quickdraw

Achievements

Achievement: Quickdraw

Block or report Princyjf

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Princyjf/README.md
  • 👋 Hi, I’m @Princy Joice
  • 👀 I’m interested in Vlsi design and verification
  • 🌱 I’m currently learning UVM
  • 💞️ I’m looking to collaborate on Different technologies
  • 📫 How to reach me mobile number 9500984643 email I'd [email protected]

Popular repositories Loading

  1. ivl_uvm ivl_uvm Public

    Forked from AsFigo/ivl_uvm

    Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.

    SystemVerilog 1

  2. MathLib MathLib Public

    Forked from AsFigo/MathLib

    MathLib DAC 2023 version

    SystemVerilog 1

  3. Princyjf Princyjf Public

    Config files for my GitHub profile.

  4. asfigo_sva_verilator asfigo_sva_verilator Public

    Forked from svenka3/asfigo_sva_verilator

    Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.

    SystemVerilog

  5. pyslint pyslint Public

    Forked from AsFigo/pyslint

    SystemVerilog Linter based on pyslang

    Python