Hace integration #3

rusty1968 · 2025-09-03T22:57:42Z

ASPEED HACE Hardware Acceleration Integration for Digest Server

Overview

This work enables hardware-accelerated cryptographic digest operations on ASPEED AST1060 systems using the HACE (Hash and Crypto Engine) hardware accelerator. The implementation provides both session-based streaming operations and one-shot digest computations through a unified HAL-based architecture.

Architecture

Hardware Abstraction Layer

OpenPRoT HAL Integration: Uses blocking digest traits (DigestInit, DigestOp) for hardware abstraction
Concrete Type Safety: Leverages Digest<N> types (N=8,12,16) for compile-time size validation
Backend Flexibility: Supports both ASPEED HACE hardware and mock implementations

Supported Algorithms

SHA-256: 256-bit output (Digest<8>)
SHA-384: 384-bit output (Digest<12>)
SHA-512: 512-bit output (Digest<16>)

Operation Modes

Session-based: init → multiple update → finalize pattern for streaming data
One-shot: Complete hash computation in single API call

Hardware Integration

ASPEED HACE Controller

Single Context Hardware: Hardware supports one active digest context at a time
System Control Integration: Proper clock enablement and reset deassertion via SysCon
Memory Safety: No unsafe code blocks in digest operations

Resource Management

Session Limits: Enforced based on hardware capabilities (1 concurrent session for HACE)
Controller Ownership: Clean move semantics for hardware resource management
Context Switching: Automatic controller return to available pool after operations

Memory Footprint

Resource Previous Current Reduction

Stack 4096 bytes 2048 bytes -50%
Flash 16384 bytes 12288 bytes -25%
RAM 16384 bytes 8192 bytes -50%

System Integration

Peripheral Configuration

SCU Integration: System Control Unit setup for HACE enablement

Clock Management: YCLK clock enablement for HACE operation

Reset Control: Proper HACE reset deassertion sequence

Application Integration

Task Configuration: Updated app.toml with HACE controller and SCU access

Dependency Management: Added ASPEED DDK and proposed-traits dependencies

Feature Flags: Conditional compilation for hardware vs. mock backends

Demo and Validation

HelloWorld Demo Task

Basic Functionality Demo: Demonstrates digest server operations with known test vectors
Session Management Demo: Shows multiple concurrent session handling
Error Condition Demo: Validates error handling for invalid inputs and session limits

Known Vector Validation

SHA-256 'abc' Vector: Validates against standard test vector ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad
Endianness Verification: Ensures proper big-endian hash format handling
Algorithm Coverage: Demonstrates SHA-256, SHA-384, and SHA-512 operations

QEMU Testing

AST1060 QEMU Emulation: Successfully tested on AST1060 QEMU environment
Hardware Emulation: Validates digest operations under emulated HACE hardware
System Boot: Confirms proper kernel startup and task initialization in virtualized environment

Key Technical Achievements

Memory Safety

Zero Unsafe Code: All digest operations use safe Rust abstractions
Move Semantics: Clean ownership transfer for hardware contexts
Option Wrappers: Proper handling of consumed contexts in update/finalize

Hardware Abstraction

Trait-Based Design: Hardware-agnostic implementation using OpenPRoT HAL
Capability System: Compile-time hardware capability detection
Backend Switching: Seamless transition between hardware and mock implementations

Error Handling

Comprehensive Error Types: Full coverage of digest operation failure modes
Session Validation: Robust session ID and state management
Hardware Failure Recovery: Graceful handling of hardware-level errors

Build System Integration

xtask Compatibility: Works with existing Hubris build system
Feature Flags: Clean separation between hardware and mock builds
Dependency Resolution: Proper workspace-level dependency management

This is the first version of a cryptographic service that leverages ASPEED's hardware acceleration capabilities while maintaining the safety and abstraction principles of the Hubris microkernel architecture, tested and validated in QEMU.

1. Build the firmware image: ``` $ cargo xtask dist app/ast1060-starter/app.toml $ gen_uart_booting_image.sh target/ast1060-starter/dist/default/final.bin \ target/ast1060-starter/dist/default/uart_final.bin ``` 2. Using uart_final.bin for boot from UART. 3. Using humility over jtag to verify ``` $ humility -e env.json -t ast1060 tasks humility: attached via JLink system time = 114057 ID TASK GEN PRI STATE 0 jefe 0 0 recv, notif: fault timer(T+43) 1 idle 0 5 RUNNING $ humility -e env.json -t ast1060 stackmargin humility: attached via JLink ID TASK STACKBASE STACKSIZE MAXDEPTH MARGIN 0 jefe 0x21000 1536 272 1264 1 idle 0x20c00 256 104 152 ``` Note: the humility has some bug in gdb connection. TODO: - Adding Secure Boot Header within final.bin - JTAG halt at main configured by features Signed-off-by: Troy Lee <[email protected]>

Signed-off-by: Troy Lee <[email protected]>

Initial support of ast1060

- run-qemu-debug.sh : starts QEMU and waits for gdb connection. - run-gdb-debug.sh : connects to QEMU, loads symbols.

helloworld task will send "Hello, world!\n" to uart driver task over IPC. Signed-off-by: Troy Lee <[email protected]> Update TICK speed and correctness UART divisor Signed-off-by: Troy Lee <[email protected]> Tx/rs test with UART Signed-off-by: Troy Lee <[email protected]> Add reply check for uart_recv Signed-off-by: Troy Lee <[email protected]> Using enum instead of hardcoded number Signed-off-by: Troy Lee <[email protected]> Fixes miss aligned buffer size Signed-off-by: Troy Lee <[email protected]> uart_read() with sys_borrow_read() Signed-off-by: Troy Lee <[email protected]> reduce rx data loss Signed-off-by: Troy Lee <[email protected]>

Implements a digest API package (drv-digest-api) for the Hubris microkernel, providing type-safe IPC bindings for cryptographic hash operations. This package bridges OpenProt's digest abstraction with Hubris's Idol interface definition language, enabling secure hash computations across service boundaries. Key features: - Support for SHA-2 (SHA256, SHA384, SHA512) and SHA-3 family algorithms - Session-based hash computation with proper state management - Zero-copy digest output types with const generic sizing - Detailed error handling for hardware and software failures - Generated client stubs for type-safe IPC communication The implementation follows Hubris design patterns for driver APIs and maintains compatibility with OpenProt's digest trait abstraction while leveraging Idol's RON-based interface definitions for robust inter-service communication. Files added: - drv/digest-api/Cargo.toml: Package configuration and dependencies - drv/digest-api/build.rs: Idol client stub generation - drv/digest-api/src/lib.rs: Core types, errors, and API definitions - Updates to Cargo.lock for new dependency integration

This commit integrates the digest-server into the ast1060-starter app and resolves zerocopy compatibility issues between idol-generated code and zerocopy 0.8.25. Key changes: - Add digest-server task to ast1060-starter app configuration - Implement zerocopy compatibility fix in digest-server build.rs - Post-process generated server_stub.rs to replace zerocopy_derive::* with zerocopy::* for compatibility with zerocopy 0.8.x API - Fix leased memory API usage in digest-server main.rs - Replace write_range() calls with write() for fixed-size arrays - Add proper zerocopy trait imports and ClientError import - Update helloworld task to use digest server - Add digest API integration with session-based and one-shot testing - Fix error handling to use DigestError instead of ClientError - Add proper dependency on drv-digest-api - Adjust memory allocations in app.toml - Increase digest-server RAM from 4096 to 8192 bytes - Increase digest-server stack from 2048 to 3200 bytes - Increase helloworld RAM from 2048 to 4096 bytes The digest server now provides SHA-256/384/512 cryptographic hashing services with both session-based and one-shot APIs, successfully building and linking with the ast1060-starter application. Technical details: - Resolved idol-runtime zerocopy trait compatibility by post-processing generated code to use zerocopy:: instead of zerocopy_derive:: prefixes - Fixed Leased<A, [T; N]> API usage - write_range() only exists for slices, fixed-size arrays use write(value: T) method - All compilation errors resolved, stack analysis passed

…atch - Integrate openprot-platform-mock MockDevice as hardware backend - Use static memory allocation for session data to avoid stack overflow - Support SHA-256/384/512 algorithms with session-based and oneshot APIs - Fix API compatibility with generated InOrderDigestImpl trait - Allocate 16KB RAM for digest server to accommodate session storage - Eliminate all runtime polymorphism for optimal performance The digest server now efficiently dispatches cryptographic operations to the MockDevice hardware abstraction layer using only static dispatch, providing a clean separation between server logic and hardware implementation.

…ices - Convert ServerImpl from hardcoded MockDigestDevice to generic ServerImpl<D> - Add trait bounds for DigestInit<Sha2_256/384/512> + DigestCtrlReset - Use associated type constraints to ensure Output = Digest<N> compatibility - Maintain full API compatibility while enabling hardware abstraction - Add comprehensive documentation for custom hardware device usage - Move session storage to static allocation to prevent stack overflow - Increase RAM allocation from 8KB to 16KB for larger session buffers - Successfully builds and passes all compilation checks The digest server can now work with any hardware device that implements the required openprot-hal-blocking traits, not just MockDigestDevice.

This commit introduces a new HMAC (Hash-based Message Authentication Code) API crate that follows Hubris patterns for cryptographic operations: New Components: * task/hmac-api/ - Client API crate with error types and constants * idl/hmac.idol - Idol interface definition with session-based operations * Integration with helloworld task as example usage Key Features: * Support for HMAC-SHA256, HMAC-SHA384, and HMAC-SHA512 algorithms * Session-based API for streaming operations (init/update/finalize) * One-shot operations for simple use cases * Comprehensive error handling with IdolError derive macro * Memory lease-based data transfer following Hubris IPC patterns API Design: * Algorithm-specific init/finalize operations for type safety * Maximum key length of 128 bytes, data chunks up to 1024 bytes * Fixed-size output buffers matching algorithm digest sizes * Session management with unique IDs for concurrent operations Technical Details: * Uses derive-idol-err for proper error type integration * Follows established patterns from digest-api crate * Builds successfully with cargo xtask dist system * Compatible with ARM Cortex-M targets via cross-compilation The API is designed to support both SPDM and PLDM protocol implementations that require HMAC operations for message authentication and integrity.

…text storage

- Update README.md of ast1060-starter app with instructions and TODOs. - Miscellaneous cleanup.

Refactor to single session.

…tion - Switch aspeed-ddk from 'refactor-hace' to 'hash-owned' branch for owned API support - Enable aspeed-hace feature in ast1060-starter app configuration - Fix HaceController initialization to use AST1060 peripheral instance - Add ast1060-pac dependency to digest-server for hardware access - Increase digest_server stack allocation from 3200 to 10240 bytes to handle stack usage - Add owned API optimization guide for future stack usage improvements This enables hardware-accelerated SHA operations using the ASPEED HACE controller on AST1060 hardware, with the digest server successfully building and linking. The increased stack allocation addresses measured usage of 9248 bytes during cryptographic operations. Future optimization should focus on identifying actual stack consumers beyond the hardware context structures. 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude <[email protected]>

- app/ast1060-starter/app.toml - Optimized digest_server memory allocations: - Stack: 4096 → 2048 bytes (-50%) - Flash: 16384 → 12288 bytes (-25%) - RAM: 16384 → 8192 bytes (-50%)

Fixed endianness and word order in expected hash comparison. The test was incorrectly using little-endian conversion and wrong word ordering for the known SHA-256 vector of 'abc'. Now properly validates against ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad. 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude <[email protected]>

* add mctp serial transport binding Signed-off-by: leongross <[email protected]> * wip * use ast1060 uart lib for uart Signed-off-by: leongross <[email protected]> --------- Signed-off-by: leongross <[email protected]> Signed-off-by: Marvin Gudel <[email protected]> Co-authored-by: leongross <[email protected]>

LeeTroy and others added 20 commits July 31, 2025 02:22

Update per comment

d7466d2

Signed-off-by: Troy Lee <[email protected]>

Merge pull request #1 from LeeTroy/ast1060-initial

bab4c30

Initial support of ast1060

fix gdb script generation

d72b85b

[test] Utilties for QEMU debug workflow.

c6527cc

- run-qemu-debug.sh : starts QEMU and waits for gdb connection. - run-gdb-debug.sh : connects to QEMU, loads symbols.

Update Cargo.lock

0d1d268

Update Cargo.lock

2806c3a

[test] Digest Server IPC test-suite

5401f73

Align implementation to the Digest Server design using persistent con…

96407ae

…text storage

[doc] + [test]

8266e8e

- Update README.md of ast1060-starter app with instructions and TODOs. - Miscellaneous cleanup.

[feat] Optimization

32fb19b

Refactor to single session.

- Updated aspeed-ddk dependency to rusty1968 fork.

ed9406f

- app/ast1060-starter/app.toml - Optimized digest_server memory allocations: - Stack: 4096 → 2048 bytes (-50%) - Flash: 16384 → 12288 bytes (-25%) - RAM: 16384 → 8192 bytes (-50%)

rusty1968 requested a review from FerralCoder September 3, 2025 22:58

FerralCoder approved these changes Sep 3, 2025

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rusty1968 requested a review from moidx September 3, 2025 23:09

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Hace integration #3

Hace integration #3

rusty1968 commented Sep 3, 2025 •

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ASPEED HACE Hardware Acceleration Integration for Digest Server

Overview

Architecture

Hardware Abstraction Layer

Supported Algorithms

Operation Modes

Hardware Integration

ASPEED HACE Controller

Resource Management

Memory Footprint

System Integration

Peripheral Configuration

Application Integration

Demo and Validation

HelloWorld Demo Task

Known Vector Validation

QEMU Testing

Key Technical Achievements

Memory Safety

Hardware Abstraction

Error Handling

Build System Integration

Uh oh!

Reviewers

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Labels

Projects

Milestone

Development

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3 participants

rusty1968 commented Sep 3, 2025 •

edited

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