[Feature] support for 2 EMIF parameter groups (#1582)

* First update for generic params (top and loc files)

* Added generic parameter support

* Updated pinout to use non array interfaces

* Add dbi back to all interfaces

* Made dbi and dqs width dynamic

* Fixed copy/paste error in interface definitions

* Added parameter group support up to 8 param groups

* Reduced parameter group support from 8 to 2

* Fixed pinouts

* Fixed ifdef typo

* updating unit test and uvm tb for add non-uniform ddr mem

* Added param group dqs identifier parameters

* Made 8G RDIMM the default for iseries-dk

* updating tb code to loop

* Interleave emif group 1 at pinout instead of interface

* adding hooks to compile legacy iseries-dk with udimm

* updating the TB

* Changed grp to group in pinout

* reverting fseries-dk pin assignment comments

* Added "USE_DBI" and made emif interfaces generic

* reducing macro used in DDR

---------

Co-authored-by: nahid hassan <[email protected]>
Co-authored-by: Nahid Hassan <[email protected]>

README.md

@@ -69,6 +69,11 @@ Work directory names in the commands below are merely examples and may be change
     ```bash
         ./ofs-common/scripts/common/syn/build_top.sh -p --ofss tools/ofss_config/pcie/pcie_host_2link_1pf_1vf.ofss iseries-dk:no_hssi,pr_floorplan=syn/board/iseries-dk/setup/pr_assignments_slim.tcl work_iseries-dk_slim
     ```
+
+    - Emif configured to use UDIMM (Instead of RDIMM that ships with the devkit):
+    ```bash
+        ./ofs-common/scripts/common/syn/build_top.sh -p --ofss tools/ofss_config/memory/memory_rtile.ofss iseries-dk:emif_udimm_pin_assn work_iseries-dk
+    ```
 
 * mseries-dk
    - Compiling the mseries-dk design requires .ofss for changing the .ip configuration. Uses NOC & HBM and works only in flat compile

ipss/mem/mem_design_files.tcl

@@ -4,6 +4,7 @@
 set vlog_macros [get_all_global_assignments -name VERILOG_MACRO]
 set include_mss 0
 set include_hbm 0
+set ddr4_num_mem_groups 1
 
 foreach_in_collection assignment [get_all_global_assignments -name DEVICE] {
     set opn [lindex $assignment 2]
@@ -25,6 +26,16 @@ foreach_in_collection m $vlog_macros {
             set include_mss 1
         }
     }
+
+    # DDR4_NUM_MEM_GROUPS has a value, so it looks like a list
+    if { [string match "DDR4_NUM_MEM_GROUPS*" [lindex $m 2]] } {
+        # Backward compatibility (UDIMM) variant to skip mutliple groups
+        if { ![info exist env(OFS_BUILD_TAG_EMIF_UDIMM_PIN_ASSN) ] } {
+            set mem_group_str [split [lindex $m 2] "="]
+            set ddr4_num_mem_groups [lindex $mem_group_str 1]
+        }
+    }
+
     if { [string equal "INCLUDE_HBM" [lindex $m 2]] } {
         # Piggy back on the DDR APP channels for now
         set_global_assignment -name VERILOG_MACRO "INCLUDE_LOCAL_MEM"
@@ -38,6 +49,11 @@ if {$include_mss == 1} {
     # Used only in simulation. Loading it here adds ed_sim_mem to the simulation environment.
     # It is not instantiated on HW.
     set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/mem/qip/ed_sim/ed_sim_mem.ip
+
+    # Adding ed_sim_model for other non-uniform groups. Not needed if
+    for {set mem_group_idx 1} {$mem_group_idx < $ddr4_num_mem_groups} {incr mem_group_idx} {
+        set_global_assignment -name IP_FILE $::env(BUILD_ROOT_REL)/ipss/mem/qip/ed_sim/ed_sim_mem_group${mem_group_idx}.ip
+    }
 
     # Add the Memory Subsystem to the dictionary of IP files that will be parsed by OFS
     # into the project's ofs_ip_cfg_db directory. Parameters from the configured

sim/bfm/ofs_axis_bfm/top_tb.sv

@@ -8,10 +8,10 @@
 //   Top level testbench with OFS top level module instantiated as DUT
 //
 //-----------------------------------------------------------------------------
-
 `include "vendor_defines.vh"
 `include "fpga_defines.vh"
 `include "ofs_ip_cfg_db.vh"
+`include "ofs_fim_mem_defines.vh"
 
 import ofs_fim_cfg_pkg::*;
 import ofs_fim_if_pkg::*;
@@ -92,7 +92,15 @@ end
 
 `ifdef INCLUDE_LOCAL_MEM
 `ifdef INCLUDE_DDR4
-   ofs_fim_emif_ddr4_if ddr4_mem [ofs_fim_mem_if_pkg::NUM_MEM_CHANNELS-1:0] ();
+
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
+   ofs_fim_emif_ddr4_if ddr4_mem [ofs_fim_mem_if_pkg::NUM_GROUP_0_DDR4_CHANNELS-1:0] ();
+`endif // OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+   ofs_fim_emif_ddr4_group_1_if ddr4_mem_group_1 [ofs_fim_mem_if_pkg::NUM_GROUP_1_DDR4_CHANNELS-1:0] ();
+`endif // OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+
+
 `ifdef INCLUDE_HPS
    ofs_fim_hps_ddr4_if  ddr4_hps (); 
  `endif
@@ -147,7 +155,15 @@ top DUT (
 
 `ifdef INCLUDE_LOCAL_MEM
 `ifdef INCLUDE_DDR4
-   .ddr4_mem     (ddr4_mem),
+
+//Fabric DDR4
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
+      .ddr4_mem  (ddr4_mem),
+`endif
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+      .ddr4_mem_group_1  (ddr4_mem_group_1),
+`endif
+
 `ifdef INCLUDE_HPS
    .ddr4_hps     (ddr4_hps),
 `endif
@@ -236,31 +252,38 @@ top DUT (
    initial ddr4_hps.ref_clk = '0;
 `endif
    genvar ch;
+
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_EN_MEM_0
    generate
-      for(ch=0; ch < ofs_fim_mem_if_pkg::NUM_MEM_CHANNELS; ch = ch+1) begin : mem_model
+      for(ch=0; ch < ofs_fim_mem_if_pkg::NUM_GROUP_0_DDR4_CHANNELS; ch = ch+1) begin : mem_model
          initial ddr4_mem[ch].ref_clk = '0;
          always #833 ddr4_mem[ch].ref_clk = ~ddr4_mem[ch].ref_clk; // 1200 MHz
-         ed_sim_mem ddr_mem_inst (
-            .mem_ck     (ddr4_mem[ch].ck),
-            .mem_ck_n   (ddr4_mem[ch].ck_n),
-            .mem_a      (ddr4_mem[ch].a),
-            .mem_act_n  (ddr4_mem[ch].act_n),
-            .mem_ba     (ddr4_mem[ch].ba),
-            .mem_bg     (ddr4_mem[ch].bg),
-            .mem_cke    (ddr4_mem[ch].cke),
-            .mem_cs_n   (ddr4_mem[ch].cs_n),
-            .mem_odt    (ddr4_mem[ch].odt),
-            .mem_reset_n(ddr4_mem[ch].reset_n),
-            .mem_par    (ddr4_mem[ch].par),
-            .mem_alert_n(ddr4_mem[ch].alert_n),
-            .mem_dqs    (ddr4_mem[ch].dqs),
-            .mem_dqs_n  (ddr4_mem[ch].dqs_n),
-            .mem_dq     (ddr4_mem[ch].dq),
-            .mem_dbi_n  (ddr4_mem[ch].dbi_n)
+
+          ed_sim_mem ddr_mem (
+         `CONNECT_DDR4_MODEL_TB(mem, mem, ddr4_mem[ch], GROUP_0)
+          );
+
+      end
+   endgenerate
+`endif //OFS_FIM_IP_CFG_LOCAL_MEM_EN_MEM_0
+
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+   generate
+      for(ch=0; ch < ofs_fim_mem_if_pkg::NUM_GROUP_1_DDR4_CHANNELS; ch = ch+1) begin : mem_model_grp1
+         initial ddr4_mem_group_1[ch].ref_clk = '0;
+         always #833 ddr4_mem_group_1[ch].ref_clk = ~ddr4_mem_group_1[ch].ref_clk; // 1200 MHz
+
+         ed_sim_mem_group1 ddr_mem_group_1 (
+         `CONNECT_DDR4_MODEL_TB(mem, mem, ddr4_mem_group_1[ch], GROUP_1)
          );
+
       end
    endgenerate
-`endif
+`endif //OFS_FIM_IP_CFG_LOCAL_MEM_EN_MEM_1
+
+
+`endif //DDR
+
 `ifdef INCLUDE_HBM
    initial uib_refclk      = '{default:'0};
    initial noc_ctrl_refclk = '{default:'0};

src/top/top.sv

@@ -32,24 +32,28 @@ module top
    import ofs_fim_eth_if_pkg::*;
  `endif
 (
-                    input                                       SYS_REFCLK                        ,// System Reference Clock (100MHz)
+                    input                                       SYS_REFCLK,   // System Reference Clock (100MHz)
 
 // Local Memory technology interfaces
 `ifdef INCLUDE_LOCAL_MEM
 `ifdef INCLUDE_DDR4
-                    ofs_fim_emif_ddr4_if.emif                      ddr4_mem     [NUM_DDR4_CHANNELS-1:0]      ,// EMIF DDR4 x32 RDIMM (x8)
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
+                     ofs_fim_emif_ddr4_if.emif                 ddr4_mem          [NUM_GROUP_0_DDR4_CHANNELS-1:0],
+`endif // OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+                     ofs_fim_emif_ddr4_group_1_if.emif         ddr4_mem_group_1     [NUM_GROUP_1_DDR4_CHANNELS-1:0],
+`endif // OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
 `ifdef INCLUDE_HPS
-                    ofs_fim_hps_ddr4_if.emif                       ddr4_hps                          ,
-`endif
-`endif
-
+                     ofs_fim_hps_ddr4_if.emif                  ddr4_hps,
+`endif // INCLUDE_HPS
+`endif // INCLUDE_DDR4
 `ifdef INCLUDE_HBM
-   input       hbm_cattrip     [NUM_HBM_DEVICES-1:0],
-   input [2:0] hbm_temp        [NUM_HBM_DEVICES-1:0],
-   input       uib_refclk      [NUM_HBM_DEVICES-1:0],
-   input       noc_ctrl_refclk [NUM_HBM_DEVICES-1:0],
-`endif
-`endif
+                     input                                     hbm_cattrip       [NUM_HBM_DEVICES-1:0],
+                     input [2:0]                               hbm_temp          [NUM_HBM_DEVICES-1:0],
+                     input                                     uib_refclk        [NUM_HBM_DEVICES-1:0],
+                     input                                     noc_ctrl_refclk   [NUM_HBM_DEVICES-1:0],
+`endif // INCLUDE_HBM
+`endif // INCLUDE_LOCAL_MEM
 
 `ifdef INCLUDE_HSSI                                                                              
                     //QSFP control signals
@@ -1225,8 +1229,13 @@ endgenerate
        // AFU ext mem interfaces
       .afu_mem_if   (afu_ext_mem_if),
 `ifdef INCLUDE_DDR4
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_0
       .ddr4_mem_if  (ddr4_mem),
 `endif
+`ifdef OFS_FIM_IP_CFG_LOCAL_MEM_DEFINES_EMIF_DDR4_PARAM_GROUP_1
+      .ddr4_mem_if_group_1  (ddr4_mem_group_1),
+`endif
+`endif
 
 `ifdef INCLUDE_HBM
       // universal interface bus clk (PIN EC36)

syn/board/iseries-dk/setup/emif_loc.tcl

@@ -624,4 +624,4 @@ set_location_assignment PIN_LB54 -to ddr4_mem[3].dq[63]
 # set_location_assignment PIN_MH44 -to ddr4_mem[3].dq[68]
 # set_location_assignment PIN_MK45 -to ddr4_mem[3].dq[69]
 # set_location_assignment PIN_MD44 -to ddr4_mem[3].dq[70]
-# set_location_assignment PIN_MC45 -to ddr4_mem[3].dq[71]
+# set_location_assignment PIN_MC45 -to ddr4_mem[3].dq[71]