Skip to content

Commit

Permalink
ci: enable questa testbenches
Browse files Browse the repository at this point in the history
  • Loading branch information
NikLeberg committed Dec 21, 2023
1 parent bc7ddb1 commit 87de77c
Show file tree
Hide file tree
Showing 2 changed files with 1 addition and 1 deletion.
1 change: 1 addition & 0 deletions .github/workflows/CI.yml
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ jobs:
run: |
cd build
make questa work.top
make questa test
make clean
- name: Run Simulation (GHDL)
Expand Down
1 change: 0 additions & 1 deletion scripts/makefile.def
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,6 @@ IGNORED_FILES += ../lib/neorv32/sim/neorv32_tb.vhd
IGNORED_FILES += ../lib/neorv32/sim/uart_rx_pkg.vhd
IGNORED_FILES += ../lib/neorv32/sim/uart_rx.vhd
IGNORED_FILES += ../vhdl/vga/tb/vga_tb.vhdl
IGNORED_FILES += ../vhdl/neorv32_debug/tb/neorv32_debug_dm_smp_tb.vhdl
# Toplevel of design.
TOP ?= top

Expand Down

0 comments on commit 87de77c

Please sign in to comment.