Skip to content

[None][feat] Add routing support for the new model for both cutlass and trtllm moe backend#9792

Merged
ChristinaZ merged 2 commits intoNVIDIA:mainfrom
ChristinaZ:add_superv3_routing
Dec 16, 2025
Merged

[None][feat] Add routing support for the new model for both cutlass and trtllm moe backend#9792
ChristinaZ merged 2 commits intoNVIDIA:mainfrom
ChristinaZ:add_superv3_routing

Conversation

@ChristinaZ
Copy link
Copy Markdown
Collaborator

@ChristinaZ ChristinaZ commented Dec 8, 2025

Summary by CodeRabbit

Release Notes

  • New Features

    • Support for larger Mixture-of-Experts models with up to 512 experts.
    • Increased maximum top-k selection capacity from 10 to 22 experts.
  • Improvements

    • Enhanced routing validation and constraint checking for expert selection.
    • Stricter group-based routing requirements for improved stability.
  • Tests

    • Added comprehensive test coverage for 512-expert configurations.

✏️ Tip: You can customize this high-level summary in your review settings.

Description

Add routing support for the new model for both cutlass and trtllm moe backend

Test Coverage


pytest -s tests/unittest/_torch/thop/parallel/test_noaux_tc.py

cd cpp/build
make -j$(nproc) google-tests
./tests/unit_tests/kernels/routingKernelsTest --gtest_filter=RoutingDeepSeekKernelTest/*

PR Checklist

Please review the following before submitting your PR:

  • PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.

  • PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

  • Test cases are provided for new code paths (see test instructions)

  • Any new dependencies have been scanned for license and vulnerabilities

  • CODEOWNERS updated if ownership changes

  • Documentation updated as needed

  • Update tava architecture diagram if there is a significant design change in PR.

  • The reviewers assigned automatically/manually are appropriate for the PR.

  • Please check this after reviewing the above items as appropriate for this PR.

GitHub Bot Help

/bot [-h] ['run', 'kill', 'skip', 'reuse-pipeline'] ...

Provide a user friendly way for developers to interact with a Jenkins server.

Run /bot [-h|--help] to print this help message.

See details below for each supported subcommand.

Details

run [--reuse-test (optional)pipeline-id --disable-fail-fast --skip-test --stage-list "A10-PyTorch-1, xxx" --gpu-type "A30, H100_PCIe" --test-backend "pytorch, cpp" --add-multi-gpu-test --only-multi-gpu-test --disable-multi-gpu-test --post-merge --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" --detailed-log --debug(experimental)]

Launch build/test pipelines. All previously running jobs will be killed.

--reuse-test (optional)pipeline-id (OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.

--disable-reuse-test (OPTIONAL) : Explicitly prevent the pipeline from reusing build artifacts and skipping successful test stages from a previous pipeline. Ensure that all builds and tests are run regardless of previous successes.

--disable-fail-fast (OPTIONAL) : Disable fail fast on build/tests/infra failures.

--skip-test (OPTIONAL) : Skip all test stages, but still run build stages, package stages and sanity check stages. Note: Does NOT update GitHub check status.

--stage-list "A10-PyTorch-1, xxx" (OPTIONAL) : Only run the specified test stages. Examples: "A10-PyTorch-1, xxx". Note: Does NOT update GitHub check status.

--gpu-type "A30, H100_PCIe" (OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.

--test-backend "pytorch, cpp" (OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.

--only-multi-gpu-test (OPTIONAL) : Only run the multi-GPU tests. Note: Does NOT update GitHub check status.

--disable-multi-gpu-test (OPTIONAL) : Disable the multi-GPU tests. Note: Does NOT update GitHub check status.

--add-multi-gpu-test (OPTIONAL) : Force run the multi-GPU tests in addition to running L0 pre-merge pipeline.

--post-merge (OPTIONAL) : Run the L0 post-merge pipeline instead of the ordinary L0 pre-merge pipeline.

--extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" (OPTIONAL) : Run the ordinary L0 pre-merge pipeline and specified test stages. Examples: --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx".

--detailed-log (OPTIONAL) : Enable flushing out all logs to the Jenkins console. This will significantly increase the log volume and may slow down the job.

--debug (OPTIONAL) : Experimental feature. Enable access to the CI container for debugging purpose. Note: Specify exactly one stage in the stage-list parameter to access the appropriate container environment. Note: Does NOT update GitHub check status.

For guidance on mapping tests to stage names, see docs/source/reference/ci-overview.md
and the scripts/test_to_stage_mapping.py helper.

kill

kill

Kill all running builds associated with pull request.

skip

skip --comment COMMENT

Skip testing for latest commit on pull request. --comment "Reason for skipping build/test" is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.

reuse-pipeline

reuse-pipeline

Reuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.

@ChristinaZ ChristinaZ requested a review from a team as a code owner December 8, 2025 14:12
@ChristinaZ ChristinaZ requested a review from yuxianq December 8, 2025 14:12
@ChristinaZ ChristinaZ changed the title [feat][None]Add routing support for the new model for both cutlass and trtllm moe backend [None][feat] Add routing support for the new model for both cutlass and trtllm moe backend Dec 8, 2025
@coderabbitai
Copy link
Copy Markdown
Contributor

coderabbitai bot commented Dec 8, 2025

📝 Walkthrough

Walkthrough

The pull request extends TensorRT-LLM's MoE routing kernels to support higher expert counts (up to 512) and increased top-k values (up to 22). Changes introduce new compile-time constants, add a MaxNumTopExperts template parameter to kernel configurations, relax validation bounds, tighten group-related conditionals, and expand test coverage across C++ kernels, Python routing logic, and unit tests.

Changes

Cohort / File(s) Summary
Kernel constant and template parameter definitions
cpp/tensorrt_llm/kernels/noAuxTcKernels.cu, cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h, cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh
Introduces compile-time constants (NumNemotronExperts=512, MaxSupportedExpertCount, MaxSupportedTopExperts=22, DefaultMaxNumTopExperts=8). Adds MaxNumTopExperts_ template parameter to KernelParams struct. Renames MaxNumTopK to MaxSupportedTopExperts (value 10→22). Updates top-k kernel template signature with new MaxNumTopExperts parameter.
Core routing kernel implementations
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu, cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
Replaces hard-coded expert/top-k bounds with parameterized constants. Updates array sizing, memory access patterns, and validation checks to use new bounds. Adjusts group-based routing logic to enforce index bounds. Extends getMaxNumExperts to handle Nemotron-scale experts. Replaces MaxNumTopExperts with MaxSupportedTopExperts throughout.
Kernel launch infrastructure
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h, cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
Updates LAUNCH_ROUTING_WITH_NUM_EXPERTS_FORCE_FLOAT_INPUT macro to propagate new numTopExperts parameter through all branches. Increases DeepSeek routing validation limit from top_k≤8 to top_k≤22.
Python validation and routing logic
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp, cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp, cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp, cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
Tightens group-related condition checks from n_group != 0 to n_group > 1 (all fp4/fp8 variants). Expands allowed top_k from ≤10 to ≤22 in mxFp4BlockScaleMoe. Skips group-specific validations when n_group == 1.
Python routing implementation
tensorrt_llm/_torch/modules/fused_moe/routing.py
Updates Deepseekv3RoutingImpl.noaux_tc branch for n_group == 1: changes threshold logic from num_experts > 384 or top_k > 8 to num_experts > 512 or (top_k > 8 and top_k != 22). Replaces score masking from element-wise multiplication to torch.where with -inf assignment for masked positions.
Test coverage expansion
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp, tests/unittest/_torch/thop/parallel/test_noaux_tc.py, tests/unittest/_torch/thop/serial/test_moe.py
Adds 512-expert test configurations for DeepSeekV3 routing across parallelization modes. Expands test matrix with (512, 1, 1, 6) and (512, 1, 1, 22) parameter combinations. Increases top_k bound validation from ≤10 to ≤22. Adds new routing test case RoutingDS_SuperV3.

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~50 minutes

  • Heterogeneous changes across 15 files: Kernel implementations, validation logic, Python routing, and tests require separate reasoning for each subsystem.
  • Critical kernel modifications: RoutingDeepSeek.cu and RoutingRenormalize.cu involve intricate changes to memory indexing, bounds checking, and control flow that necessitate careful verification of correctness across expert/top-k combinations.
  • Template parameter propagation: New MaxNumTopExperts parameter threading through macro invocations and kernel signatures requires tracing consistency across multiple files.
  • Validation tightening vs. relaxation: Group conditions narrowed (n_group > 1) while top-k limits expanded (≤22), requiring verification that interactions do not create new edge cases or conflicts.

Areas requiring extra attention:

  • RoutingDeepSeek.cu: Verify bounds checking logic for 512-expert Nemotron path and updated getMaxNumExperts branching.
  • RoutingRenormalize.cu: Ensure all array indexing, shared memory writes, and validation checks use consistent new bounds (MaxSupportedTopExperts).
  • tensorrt_llm/_torch/modules/fused_moe/routing.py: Review masking change from multiplication to -inf assignment and threshold logic update (top_k != 22 special case).
  • Macro propagation in DevKernel.h: Confirm numTopExperts is threaded through all conditional branches without omission.
  • Python validation consistency: Verify n_group > 1 condition is applied uniformly across all four thop files and correctly skips group checks for n_group == 1.

Pre-merge checks and finishing touches

❌ Failed checks (1 warning)
Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 6.45% which is insufficient. The required threshold is 80.00%. You can run @coderabbitai generate docstrings to improve docstring coverage.
✅ Passed checks (2 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly identifies the main change: adding routing support for a new model across both cutlass and trtllm MoE backends, which aligns with the file summaries.
Description check ✅ Passed The pull request description is mostly complete with a clear summary and provided test coverage, though the general description could be more detailed about specific changes.
✨ Finishing touches
  • 📝 Generate docstrings
🧪 Generate unit tests (beta)
  • Create PR with unit tests
  • Post copyable unit tests in a comment

Thanks for using CodeRabbit! It's free for OSS, and your support helps us grow. If you like it, consider giving us a shout-out.

❤️ Share

Comment @coderabbitai help to get the list of available commands and usage tips.

Copy link
Copy Markdown
Contributor

@coderabbitai coderabbitai bot left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Actionable comments posted: 1

🧹 Nitpick comments (6)
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)

1-2: Update copyright year to include 2025.

As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.

 /*
- * Copyright (c) 2022-2024, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2022-2025, NVIDIA CORPORATION.  All rights reserved.
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)

1-2: Update copyright year to include 2025.

As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.

 /*
- * Copyright (c) 2022-2024, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2022-2025, NVIDIA CORPORATION.  All rights reserved.
cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)

1-2: Update copyright year to include 2025.

As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.

 /*
- * Copyright (c) 2022-2024, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2022-2025, NVIDIA CORPORATION.  All rights reserved.
tensorrt_llm/_torch/modules/fused_moe/routing.py (1)

253-301: DeepSeekV3 routing bounds and masking changes look correct; consider a tiny allocation tweak.

The updated n_group == 1 condition cleanly restricts the fused path to num_experts <= 512 and top_k <= 8 (or top_k == 22 for the Nemotron Super v3 special case), which matches the new kernel capabilities. Replacing scores_with_bias *= score_mask with torch.where(..., -inf) correctly prevents masked experts from being reselected by the subsequent top‑k.

If you want to shave a small allocation in torch.where, you could use scores_with_bias.new_full((), float('-inf')) instead of constructing a fresh scalar tensor each call, but this is a minor optimization.

cpp/tensorrt_llm/kernels/noAuxTcKernels.cu (1)

31-44: DeepSeek no‑aux top‑k kernel extensions match the new 512/22 config; document the MaxNumTopExperts invariant.

The new expert/top‑k constants, extra MaxNumTopExperts template parameter, multi‑warp shared‑memory initialization, and the invokeNoAuxTc dispatch logic (including the dedicated 512‑expert/22‑way single‑group path) are all consistent with supporting Nemotron Super v3 while preserving existing DeepSeek (≤256‑expert, top_k≤8) group behavior.

These implementations implicitly rely on topk <= MaxNumTopExperts for each instantiated kernel (8 for existing paths, 22 for the 512‑expert specialization). It would be good to keep that invariant explicit in comments or host‑side checks if new DeepSeek configs are added later, so we never accidentally launch with a larger runtime topk than the compile‑time MaxNumTopExperts.

Also applies to: 47-52, 120-129, 166-226, 273-334

cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (1)

247-366: Consider adding a test with useTopKAsInput=true for 512-expert configuration.

The new tests cover the score-based routing path well. For completeness, consider adding a test variant similar to DeviceLevelParallelization that tests the pre-computed topK path (useTopKAsInput=true) with 512 experts.

📜 Review details

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 98db262 and bf73bf5.

📒 Files selected for processing (15)
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu (6 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h (1 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu (10 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h (1 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh (1 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu (8 hunks)
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu (1 hunks)
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1 hunks)
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1 hunks)
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1 hunks)
  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (2 hunks)
  • cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (3 hunks)
  • tensorrt_llm/_torch/modules/fused_moe/routing.py (2 hunks)
  • tests/unittest/_torch/thop/parallel/test_noaux_tc.py (1 hunks)
  • tests/unittest/_torch/thop/serial/test_moe.py (2 hunks)
🧰 Additional context used
📓 Path-based instructions (5)
**/*.{cpp,h,cu}

📄 CodeRabbit inference engine (CODING_GUIDELINES.md)

**/*.{cpp,h,cu}: Closing braces of namespaces should have a comment saying the namespace it closes (e.g., } // namespace foo)
Prefer const or constexpr variables over #define whenever possible, as the latter are not visible to the compiler
A variable that is not modified after its initialization should be declared as const
Except 0 (only used in comparison for checking signness/existence/emptiness) and nullptr, true, false, all other literals should only be used for variable initialization and should be replaced with named constants
Use Allman indentation style for braces in C++
Put the semicolon for an empty for or while loop in a new line
The statement forming the body of a switch, while, do .. while or for statement shall be a compound statement (use brace-delimited statements)
If and else should always be followed by brace-delimited statements, even if empty or a single statement
C++ filenames should use camel case with first letter lowercase (e.g., thisIsASubDir and thisIsAFilename.cpp)
All filenames involved in compilation of a compilation target must have case-insensitive unique filenames
All types (including class names) should use camel case with uppercase first letter (e.g., FooBarClass)
Local variables, methods and namespaces should use camel case with first letter lowercase (e.g., localFooBar)
Non-magic-number global variables that are non-static and not defined in anonymous namespace should use camel case prefixed by a lower case 'g' (e.g., gDontUseGlobalFoos)
Non-magic-number global variables that are static or defined in an anonymous namespace should use camel case prefixed by a lower case 's' (e.g., sMutableStaticGlobal)
Locally visible static variables should use camel case with lowercase prefix 's' as the first letter of the name (e.g., static std::once_flag sFlag;)
Public, private and protected class member variables should use camel case prefixed with 'm' (e.g., mNbFooValues), though the 'm' pre...

Files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.{cpp,h,cu,py}

📄 CodeRabbit inference engine (CODING_GUIDELINES.md)

All TensorRT-LLM Open Source Software code files should contain an NVIDIA copyright header that includes the current year at the top

Files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • tests/unittest/_torch/thop/parallel/test_noaux_tc.py
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp
  • tests/unittest/_torch/thop/serial/test_moe.py
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.h

📄 CodeRabbit inference engine (CODING_GUIDELINES.md)

**/*.h: Use a preprocessor guard in C++ header files with the guard name format TRTLLM_ followed by the filename in all caps (e.g., TRTLLM_FOO_BAR_HELLO_H for file FooBarHello.h); do not include directory names in the symbol
Do not use underscore prefix or suffix in C++ preprocessor guard symbols; they are reserved in C++ standard for compilers or implementation

Files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
**/*.cu

📄 CodeRabbit inference engine (CODING_GUIDELINES.md)

CUDA code must be compiled with a CUDA compiler and includes declarations/definitions with CUDA keywords (__device__, __managed__, __constant__, __global__), device functions, and kernel launching with <<<...>>> syntax

Files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.py

📄 CodeRabbit inference engine (CODING_GUIDELINES.md)

**/*.py: The code developed for TensorRT-LLM should conform to Python 3.8+
Indent Python code with 4 spaces; do not use tabs
Always maintain the namespace when importing in Python, even if only one class or function from a module is used (e.g., use from package.subpackage import foo and then foo.SomeClass() instead of from package.subpackage.foo import SomeClass)
Python filenames should use snake_case (e.g., some_file.py)
Python class names should use PascalCase (e.g., class SomeClass)
Python function and method names should use snake_case (e.g., def my_awesome_function():)
Python local variable names should use snake_case, with prefix k for variable names that start with a number (e.g., k_99th_percentile = ...)
Python global variables should use upper snake_case with prefix G (e.g., G_MY_GLOBAL = ...)
Python constants should use upper snake_case (e.g., MY_CONSTANT = ...)
Avoid shadowing variables declared in an outer scope in Python
Initialize all externally visible members of a Python class in the constructor
For Python interfaces that may be used outside a file, prefer docstrings over comments
Python comments should be reserved for code within a function, or interfaces that are local to a file
Use Google style docstrings for Python classes and functions, which can be parsed by Sphinx
Python attributes and variables can be documented inline with type and description (e.g., self.x = 5 followed by """<type>: Description of 'x'""" )
Avoid using reflection in Python when functionality can be easily achieved without reflection
When using try-except blocks in Python, limit the except clause to the smallest set of specific errors possible instead of catching all exceptions
When using try-except blocks in Python to handle multiple possible variable types (duck-typing), keep the body of the try as small as possible and use the else block to implement the logic

Files:

  • tests/unittest/_torch/thop/parallel/test_noaux_tc.py
  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • tests/unittest/_torch/thop/serial/test_moe.py
🧠 Learnings (18)
📓 Common learnings
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-08T22:03:40.707Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-14T23:23:27.449Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-20T06:56:02.889Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6768
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:577-579
Timestamp: 2025-08-20T06:56:02.889Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, maxSequenceLength is now enforced as a non-optional argument in the BlockManager constructor, so concerns about std::nullopt defaulting to 0 are not applicable. When windowSize > maxSequenceLength, a warning should be added instead of handling optional parameter cases.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-20T07:43:36.447Z
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.

Applied to files:

  • cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.

Applied to files:

  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-14T21:04:50.248Z
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.

Applied to files:

  • cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
  • cpp/tensorrt_llm/kernels/noAuxTcKernels.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-21T02:39:12.009Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1475-1480
Timestamp: 2025-08-21T02:39:12.009Z
Learning: The min latency mode functionality in TensorRT-LLM MOE kernels (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu) is deprecated and no longer being maintained/updated, as confirmed by djns99. Bug reports and optimization suggestions for the computeStridesTmaWarpSpecializedLowLatencyKernel and related min latency code paths should be deprioritized.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.

Applied to files:

  • cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-11-14T11:22:03.729Z
Learnt from: nzmora-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 9163
File: tensorrt_llm/_torch/auto_deploy/custom_ops/quant.py:107-113
Timestamp: 2025-11-14T11:22:03.729Z
Learning: In TensorRT-LLM AutoDeploy custom ops, when adding hardware capability checks to select between kernel implementations (e.g., cuBLAS vs. CUDA kernel), use descriptive variable names that identify the specific GPU architectures or families being targeted (e.g., `is_blackwell_geforce_or_ada`) rather than generic names like `enable_cuda_core`. This makes it clear that the code is selecting an implementation path based on hardware capabilities, not enabling/disabling hardware features.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.

Applied to files:

  • tensorrt_llm/_torch/modules/fused_moe/routing.py
  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-08T04:10:19.038Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6728
File: cpp/tensorrt_llm/plugins/mixtureOfExperts/mixtureOfExpertsPlugin.cpp:966-966
Timestamp: 2025-08-08T04:10:19.038Z
Learning: TensorRT plugins currently don't support padding functionality, and TensorRT is not getting new features (in maintenance mode). This means that duplicating parameters like mExpertHiddenSize in function calls, even with TODO comments, can be acceptable as pragmatic solutions within these constraints.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.

Applied to files:

  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-26T06:07:02.166Z
Learnt from: shaharmor98
Repo: NVIDIA/TensorRT-LLM PR: 7231
File: tensorrt_llm/_torch/pyexecutor/_util.py:504-509
Timestamp: 2025-08-26T06:07:02.166Z
Learning: In tensorrt_llm/_torch/pyexecutor/_util.py, when calling model_engine.set_lora_model_config(), pass model_binding_config.mlp_hidden_size directly without multiplying by mapping.tp_size, as the mlp_hidden_size from get_bindings_model_config() is already the per-TP rank value needed for LoRA weight packaging.

Applied to files:

  • cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-25T00:03:39.294Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1185-1189
Timestamp: 2025-08-25T00:03:39.294Z
Learning: TLLM_CHECK_WITH_INFO is a host-side utility function and cannot be called from CUDA device functions (those marked with __device__ or __global__). In device code, assert() is the primary mechanism for handling "should never happen" conditions, and like standard C++ assert, CUDA's assert only works in debug builds and is compiled out in release builds.

Applied to files:

  • cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
🧬 Code graph analysis (8)
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
  • n_group (276-276)
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
  • n_group (276-276)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu (4)
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (2)
  • topK (416-417)
  • topK (502-503)
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)
  • topK (332-333)
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (2)
  • topK (496-498)
  • topK (588-590)
cpp/tests/unit_tests/kernels/routing/routingTest.h (1)
  • topK (231-231)
tensorrt_llm/_torch/modules/fused_moe/routing.py (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (2)
  • num_experts (269-269)
  • top_k (275-275)
tensorrt_llm/functional.py (1)
  • where (3043-3099)
cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
  • n_group (276-276)
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (2)
cpp/tests/unit_tests/kernels/routing/routingRenormalizeTest.cpp (6)
  • param (39-150)
  • param (39-39)
  • param (152-158)
  • param (152-152)
  • param (190-196)
  • param (190-191)
cpp/tests/unit_tests/kernels/routing/routingLlama4Test.cpp (6)
  • param (39-91)
  • param (39-39)
  • param (93-99)
  • param (93-93)
  • param (120-126)
  • param (120-121)
tests/unittest/_torch/thop/serial/test_moe.py (1)
tensorrt_llm/_torch/modules/fused_moe/routing.py (2)
  • RoutingMethodType (147-159)
  • top_k (362-363)
cpp/tensorrt_llm/kernels/noAuxTcKernels.cu (3)
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (2)
  • x (42-45)
  • x (42-42)
cpp/tests/unit_tests/kernels/routing/routingTest.h (1)
  • topkGroup (256-256)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (2)
  • n_group (276-276)
  • topk_group (278-278)
⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)
  • GitHub Check: Pre-commit Check
🔇 Additional comments (29)
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)

105-118: Condition change looks correct.

Changing from n_group.value() != 0 to n_group.value() > 1 is semantically appropriate: when n_group == 1, all experts belong to a single group, making group-based routing checks unnecessary. This aligns with the default n_group{0} in runner.h:275 which also indicates "no grouping."

cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)

107-120: LGTM!

The condition change is consistent with the other MoE files in this PR and correctly gates group-based routing checks to only apply when n_group > 1.

cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (1)

115-128: LGTM!

The condition change correctly gates the group-based routing validation to only apply when there are multiple groups (n_group > 1).

cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)

108-121: LGTM!

The condition change is consistent with the other MoE files in this PR and correctly restricts group-based routing validation to multi-group scenarios only.

tests/unittest/_torch/thop/parallel/test_noaux_tc.py (1)

8-14: New 512‑expert/top‑k test cases look consistent.

The added (512, 1, 1, 6) and (512, 1, 1, 22) combinations align with the new DeepSeek V3 single‑group routing support and exercise the extended kernel space without changing test logic.

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h (1)

185-220: Macro extension for numTopExperts is wired through consistently.

The extra numTopExperts parameter is plumbed through all dtype/flag branches of LAUNCH_ROUTING_WITH_NUM_EXPERTS_FORCE_FLOAT_INPUT and into LAUNCH_TILEN’s type pack, matching the new KernelParams<..., MaxNumTopExperts_, ...> template shape.

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h (1)

192-235: KernelParams now exposes MaxNumTopExperts cleanly.

Adding MaxNumTopExperts_ to the DeepSeek KernelParams template and surfacing it as static constexpr int MaxNumTopExperts aligns the struct with the updated launch macros and no‑aux top‑k kernels without affecting existing data wiring.

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu (1)

70-108: DeepSeek top‑k validation now matches kernel capacity.

Relaxing the DeepSeek routing check from topK <= 8 to topK <= 22 is consistent with the new MaxSupportedTopExperts bound and the 512‑expert/22‑way specialization, while still guarding against unsupported larger values.

tests/unittest/_torch/thop/serial/test_moe.py (1)

994-1066: FP4 MoE tests are ready for the 512‑expert/22‑way DeepSeek configuration.

The new RoutingDS_SuperV3 entry (512 experts, top_k=22, n_groups=1) and the relaxed assert top_k <= 22 in run_moe_fp4_test line up with the extended DeepSeek routing kernels. Once the skip around test_autotune is removed, this will exercise the new Nemotron Super v3 path end‑to‑end.

Would you like to also add a similar top‑k≤22 guard in any future FP8‑FP4 or per‑tensor FP8 tests if you plan to run 512/22 there as well, to keep test helpers consistent?

Also applies to: 1253-1255

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh (1)

36-39: MaxSupportedTopExperts constant correctly reflects the new 22‑way cap.

Renaming the top‑k bound to MaxSupportedTopExperts and raising it to 22 keeps this header in sync with the updated routing kernels and runner checks for extended DeepSeek configurations.

cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (3)

247-256: LGTM! New 512-expert test for cluster-level parallelization.

The test parameters are consistent with the existing patterns for non-grouped tests (like ClusterLevelParallelization384), and topK=22 aligns with the new MaxSupportedTopExperts constant.


324-333: LGTM! New 512-expert test for cooperative-level parallelization.

Parameters follow the established cooperative-level test patterns with appropriate compute capability requirement.


357-366: LGTM! New 512-expert test for device-level parallelization.

Test appropriately uses the score-based routing path (useTopKAsInput=false), consistent with the DeviceLevelParallelization384 test pattern.

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu (11)

26-34: LGTM! Well-defined constants for Nemotron model support.

The new constants clearly establish the 512-expert capacity and 22 top-K limit. Using std::max for MaxSupportedExpertCount is a clean approach that will automatically adapt if new expert counts are added.


130-131: LGTM! Arrays properly parameterized by template.

Using KernelParams::MaxNumTopExperts for array sizes allows different kernel instantiations to optimize for their specific top-K requirements.


168-171: LGTM! Proper bounds checking for limited groups.

The additional conditions (ii < params.mNumLimitedGroups) && (groupIdx < params.mNumExpertGroups) correctly prevent out-of-bounds access when fewer than MaxNumTopGroups groups are in use.


182-209: LGTM! Correct handling of intermediate top-K storage.

The shared memory sizing and indexing are correctly parameterized. The new initialization of unused slots (lines 204-208) with invalidScoreFloat ensures clean reduction when mTopK < MaxNumTopExperts.


214-233: LGTM! Correct work distribution for final reduction.

The NumInterTopKPerThread calculation correctly determines how many intermediate results each lane processes during the final warp-level reduction.


305-306: LGTM! Template parameter correctly propagated.

The routingPermutation template invocation correctly uses KernelParams::MaxNumTopExperts for consistency.


569-577: LGTM! Correctly extends expert count tiers.

The new branch for NumNemotronExperts (512) is correctly placed in ascending order after the 384-expert tier.


598-609: LGTM! Efficient top-K size selection for Nemotron.

The conditional dispatch based on mTopK allows using smaller arrays (DefaultMaxNumTopExperts=8) when top-K is small, avoiding unnecessary memory overhead when the full 22-element capacity isn't needed.


664-669: LGTM! Validation bounds correctly updated.

The validation checks are appropriate:

  • numExperts >= MaxSupportedTopExperts ensures top-K can be supported
  • numExperts <= MaxSupportedExpertCount enforces the 512-expert limit
  • topK <= MaxSupportedTopExperts enforces the 22 top-K limit

695-700: LGTM! Thread count calculation handles both routing modes.

The max() correctly selects sufficient threads for either grouped routing (based on expert groups) or non-grouped routing (based on expert count).


688-692: The conditional placement of the numExperts % 4 check is correct and properly scoped.

TensorRT-LLM uses two distinct kernel implementations: grouped routing uses optimized grouped GEMM kernels (when numExpertGroups > 1), while non-grouped routing uses simpler per-expert/merged kernels (when numExpertGroups == 1). The % 4 divisibility constraint applies specifically to the grouped GEMM kernels' per-thread expert processing. Since non-grouped routing uses a different kernel family without this constraint, the conditional placement is appropriate.

Likely an incorrect or invalid review comment.

cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu (5)

28-28: LGTM! Renamed constant for clarity.

Renaming MaxNumTopExperts to MaxSupportedTopExperts improves clarity and aligns with the naming convention used in RoutingDeepSeek.cu. The value (10) remains appropriate for the renormalize routing path.


35-39: LGTM! Function signature clearly documents array bounds.

The explicit MaxSupportedTopExperts sizing in the function parameters makes the array size requirements clear to callers.


152-153: LGTM! Consistent naming throughout kernel functions.

All top-K array declarations consistently use the renamed MaxSupportedTopExperts constant.


359-365: LGTM! Template parameters correctly updated.

Both routingPermutation invocations use the renamed MaxSupportedTopExperts template parameter.


489-490: LGTM! Validation check uses renamed constant.

The top-K validation correctly uses MaxSupportedTopExperts with an informative error message.

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27414 [ run ] triggered by Bot. Commit: 82e5175

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27414 [ run ] completed with state SUCCESS. Commit: 82e5175
/LLM/main/L0_MergeRequest_PR pipeline #20946 completed with status: 'FAILURE'

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27670 [ run ] triggered by Bot. Commit: 4d4cff0

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27670 [ run ] completed with state SUCCESS. Commit: 4d4cff0
/LLM/main/L0_MergeRequest_PR pipeline #21123 completed with status: 'FAILURE'

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27698 [ run ] triggered by Bot. Commit: 4d4cff0

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27698 [ run ] completed with state SUCCESS. Commit: 4d4cff0
/LLM/main/L0_MergeRequest_PR pipeline #21145 completed with status: 'FAILURE'

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27797 [ run ] triggered by Bot. Commit: bbfde9c

Signed-off-by: Yue Weng <25103990+yweng0828@users.noreply.github.com>

Added Top‑22 support for DeepSeek mode routing in the MoE TRTLLM‑GEN backend

Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27814 [ run ] triggered by Bot. Commit: 223942c

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27814 [ run ] completed with state ABORTED. Commit: 223942c
LLM/main/L0_MergeRequest_PR #21229 (Blue Ocean) completed with status: ABORTED

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27999 [ run ] triggered by Bot. Commit: 223942c

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #27999 [ run ] completed with state SUCCESS. Commit: 223942c
/LLM/main/L0_MergeRequest_PR pipeline #21382 completed with status: 'FAILURE'

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28250 [ run ] triggered by Bot. Commit: 223942c

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28250 [ run ] completed with state SUCCESS. Commit: 223942c
/LLM/main/L0_MergeRequest_PR pipeline #21603 completed with status: 'SUCCESS'

@ChristinaZ ChristinaZ enabled auto-merge (squash) December 15, 2025 02:50
@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28320 [ run ] triggered by Bot. Commit: ccd8c3e

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28320 [ run ] completed with state SUCCESS. Commit: ccd8c3e
/LLM/main/L0_MergeRequest_PR pipeline #21665 completed with status: 'FAILURE'

@ChristinaZ
Copy link
Copy Markdown
Collaborator Author

/bot run --disable-fail-fast

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28479 [ run ] triggered by Bot. Commit: ccd8c3e

@tensorrt-cicd
Copy link
Copy Markdown
Collaborator

PR_Github #28479 [ run ] completed with state SUCCESS. Commit: ccd8c3e
/LLM/main/L0_MergeRequest_PR pipeline #21808 completed with status: 'SUCCESS'

@ChristinaZ ChristinaZ merged commit dff77ef into NVIDIA:main Dec 16, 2025
5 checks passed
sherry-1001 pushed a commit to sherry-1001/TensorRT-LLM that referenced this pull request Dec 16, 2025
…nd trtllm moe backend (NVIDIA#9792)

Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
codego7250 pushed a commit to codego7250/TensorRT-LLM that referenced this pull request Dec 19, 2025
…nd trtllm moe backend (NVIDIA#9792)

Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
yzh119 pushed a commit to flashinfer-ai/flashinfer that referenced this pull request Jan 30, 2026
…ron (#2304)

<!-- .github/pull_request_template.md -->

## 📌 Description

- Support element wise activation (relu^2) in fused MoE in NVFP4 and in
FP8PerTensor.
  - Use new `ActivationType` enum class instead of `GatedActType`.
- Support Nemotron in deepseek routing as in
NVIDIA/TensorRT-LLM#9792
- Remove 'A' suffix from `UseShuffledMatrixA`

## 🔍 Related Issues

<!-- Link any related issues here -->

## 🚀 Pull Request Checklist

Thank you for contributing to FlashInfer! Before we review your pull
request, please make sure the following items are complete.

### ✅ Pre-commit Checks

- [x] I have installed `pre-commit` by running `pip install pre-commit`
(or used your preferred method).
- [x] I have installed the hooks with `pre-commit install`.
- [x] I have run the hooks manually with `pre-commit run --all-files`
and fixed any reported issues.

> If you are unsure about how to set up `pre-commit`, see [the
pre-commit documentation](https://pre-commit.com/).

## 🧪 Tests

- [ ] Tests have been added or updated as needed.
- [ ] All tests are passing (`unittest`, etc.).

## Reviewer Notes

<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.
-->


<!-- This is an auto-generated comment: release notes by coderabbit.ai
-->
## Summary by CodeRabbit

* **New Features**
* Expanded activation options (Gelu, Relu, Silu, Swiglu, Geglu,
SwigluBias, Relu2, Identity) and exposed ActivationType throughout the
CLI and APIs.
* DeepSeek routing supports larger top‑K and a configurable top‑experts
dimension.
* Added post‑GEMM element‑wise activation option and a CLI flag to
select activation type.

* **Breaking Changes**
* ActivationType replaces the previous gated-activation enum in public
APIs and tests; callers must use ActivationType values.

<sub>✏️ Tip: You can customize this high-level summary in your review
settings.</sub>
<!-- end of auto-generated comment: release notes by coderabbit.ai -->

---------

Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
yzh119 pushed a commit to flashinfer-ai/flashinfer that referenced this pull request Feb 4, 2026
…ron, fixed (#2462)

<!-- .github/pull_request_template.md -->

## 📌 Description

- Support element wise activation (relu^2) in fused MoE in NVFP4 and in
FP8PerTensor.
- Use new ActivationType enum class instead of GatedActType.
- Support Nemotron in deepseek routing as in
NVIDIA/TensorRT-LLM#9792
- Remove 'A' suffix from UseShuffledMatrixA.

NOTE: This is the fixed version of
#2304 that was merged
and reverted.
- Replaced the problematic condition in deepseek routing that required
`NumExperts >= MaxSupportedTopExperts` with `topK<=numExperts`
  - DeepSeek R1 works with it (tested with VLLM).
- Removed irrelevant test cases.


## 🔍 Related Issues

<!-- Link any related issues here -->

## 🚀 Pull Request Checklist

Thank you for contributing to FlashInfer! Before we review your pull
request, please make sure the following items are complete.

### ✅ Pre-commit Checks

- [x] I have installed `pre-commit` by running `pip install pre-commit`
(or used your preferred method).
- [x] I have installed the hooks with `pre-commit install`.
- [x] I have run the hooks manually with `pre-commit run --all-files`
and fixed any reported issues.

> If you are unsure about how to set up `pre-commit`, see [the
pre-commit documentation](https://pre-commit.com/).

## 🧪 Tests

- [ ] Tests have been added or updated as needed.
- [ ] All tests are passing (`unittest`, etc.).

## Reviewer Notes

<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.
-->


<!-- This is an auto-generated comment: release notes by coderabbit.ai
-->
## Summary by CodeRabbit

* **Refactor**
* Replaced old gated-activation API with a unified ActivationType enum
(many activation kinds supported).
  * Propagated activation_type across MoE workflows and kernels.

* **New Features**
* Added CLI option --activation-type to select activation kind for MoE
benchmarks.

* **Bug Fixes**
  * Enforced activation compatibility and validation for FP8/FP4 paths.

* **Tests**
* Updated and expanded tests to cover new activation types and
compatibility scenarios.
<!-- end of auto-generated comment: release notes by coderabbit.ai -->

---------

Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
raayandhar pushed a commit to raayandhar/flashinfer that referenced this pull request Feb 5, 2026
…ron, fixed (flashinfer-ai#2462)

<!-- .github/pull_request_template.md -->

## 📌 Description

- Support element wise activation (relu^2) in fused MoE in NVFP4 and in
FP8PerTensor.
- Use new ActivationType enum class instead of GatedActType.
- Support Nemotron in deepseek routing as in
NVIDIA/TensorRT-LLM#9792
- Remove 'A' suffix from UseShuffledMatrixA.

NOTE: This is the fixed version of
flashinfer-ai#2304 that was merged
and reverted.
- Replaced the problematic condition in deepseek routing that required
`NumExperts >= MaxSupportedTopExperts` with `topK<=numExperts`
  - DeepSeek R1 works with it (tested with VLLM).
- Removed irrelevant test cases.


## 🔍 Related Issues

<!-- Link any related issues here -->

## 🚀 Pull Request Checklist

Thank you for contributing to FlashInfer! Before we review your pull
request, please make sure the following items are complete.

### ✅ Pre-commit Checks

- [x] I have installed `pre-commit` by running `pip install pre-commit`
(or used your preferred method).
- [x] I have installed the hooks with `pre-commit install`.
- [x] I have run the hooks manually with `pre-commit run --all-files`
and fixed any reported issues.

> If you are unsure about how to set up `pre-commit`, see [the
pre-commit documentation](https://pre-commit.com/).

## 🧪 Tests

- [ ] Tests have been added or updated as needed.
- [ ] All tests are passing (`unittest`, etc.).

## Reviewer Notes

<!-- Optional: anything you'd like reviewers to focus on, concerns, etc.
-->


<!-- This is an auto-generated comment: release notes by coderabbit.ai
-->
## Summary by CodeRabbit

* **Refactor**
* Replaced old gated-activation API with a unified ActivationType enum
(many activation kinds supported).
  * Propagated activation_type across MoE workflows and kernels.

* **New Features**
* Added CLI option --activation-type to select activation kind for MoE
benchmarks.

* **Bug Fixes**
  * Enforced activation compatibility and validation for FP8/FP4 paths.

* **Tests**
* Updated and expanded tests to cover new activation types and
compatibility scenarios.
<!-- end of auto-generated comment: release notes by coderabbit.ai -->

---------

Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants