[None][feat] Add routing support for the new model for both cutlass and trtllm moe backend#9792
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📝 WalkthroughWalkthroughThe pull request extends TensorRT-LLM's MoE routing kernels to support higher expert counts (up to 512) and increased top-k values (up to 22). Changes introduce new compile-time constants, add a Changes
Estimated code review effort🎯 4 (Complex) | ⏱️ ~50 minutes
Areas requiring extra attention:
Pre-merge checks and finishing touches❌ Failed checks (1 warning)
✅ Passed checks (2 passed)
✨ Finishing touches
🧪 Generate unit tests (beta)
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Actionable comments posted: 1
🧹 Nitpick comments (6)
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)
1-2: Update copyright year to include 2025.As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.
/* - * Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)
1-2: Update copyright year to include 2025.As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.
/* - * Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)
1-2: Update copyright year to include 2025.As per coding guidelines, all TensorRT-LLM OSS code files should include the current year in the copyright header.
/* - * Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.tensorrt_llm/_torch/modules/fused_moe/routing.py (1)
253-301: DeepSeekV3 routing bounds and masking changes look correct; consider a tiny allocation tweak.The updated
n_group == 1condition cleanly restricts the fused path tonum_experts <= 512andtop_k <= 8(ortop_k == 22for the Nemotron Super v3 special case), which matches the new kernel capabilities. Replacingscores_with_bias *= score_maskwithtorch.where(..., -inf)correctly prevents masked experts from being reselected by the subsequent top‑k.If you want to shave a small allocation in
torch.where, you could usescores_with_bias.new_full((), float('-inf'))instead of constructing a fresh scalar tensor each call, but this is a minor optimization.cpp/tensorrt_llm/kernels/noAuxTcKernels.cu (1)
31-44: DeepSeek no‑aux top‑k kernel extensions match the new 512/22 config; document the MaxNumTopExperts invariant.The new expert/top‑k constants, extra
MaxNumTopExpertstemplate parameter, multi‑warp shared‑memory initialization, and theinvokeNoAuxTcdispatch logic (including the dedicated 512‑expert/22‑way single‑group path) are all consistent with supporting Nemotron Super v3 while preserving existing DeepSeek (≤256‑expert, top_k≤8) group behavior.These implementations implicitly rely on
topk <= MaxNumTopExpertsfor each instantiated kernel (8 for existing paths, 22 for the 512‑expert specialization). It would be good to keep that invariant explicit in comments or host‑side checks if new DeepSeek configs are added later, so we never accidentally launch with a larger runtimetopkthan the compile‑timeMaxNumTopExperts.Also applies to: 47-52, 120-129, 166-226, 273-334
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (1)
247-366: Consider adding a test withuseTopKAsInput=truefor 512-expert configuration.The new tests cover the score-based routing path well. For completeness, consider adding a test variant similar to
DeviceLevelParallelizationthat tests the pre-computed topK path (useTopKAsInput=true) with 512 experts.
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📒 Files selected for processing (15)
cpp/tensorrt_llm/kernels/noAuxTcKernels.cu(6 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h(1 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu(10 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h(1 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh(1 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu(8 hunks)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu(1 hunks)cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp(1 hunks)cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp(1 hunks)cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp(1 hunks)cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp(2 hunks)cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp(3 hunks)tensorrt_llm/_torch/modules/fused_moe/routing.py(2 hunks)tests/unittest/_torch/thop/parallel/test_noaux_tc.py(1 hunks)tests/unittest/_torch/thop/serial/test_moe.py(2 hunks)
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Files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cppcpp/tensorrt_llm/kernels/noAuxTcKernels.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.{cpp,h,cu,py}
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
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Files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cutests/unittest/_torch/thop/parallel/test_noaux_tc.pycpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.htensorrt_llm/_torch/modules/fused_moe/routing.pycpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpptests/unittest/_torch/thop/serial/test_moe.pycpp/tensorrt_llm/kernels/noAuxTcKernels.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.h
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
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Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
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Files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/kernels/noAuxTcKernels.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
**/*.py
📄 CodeRabbit inference engine (CODING_GUIDELINES.md)
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Files:
tests/unittest/_torch/thop/parallel/test_noaux_tc.pytensorrt_llm/_torch/modules/fused_moe/routing.pytests/unittest/_torch/thop/serial/test_moe.py
🧠 Learnings (18)
📓 Common learnings
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuhcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.htensorrt_llm/_torch/modules/fused_moe/routing.pycpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-08T22:03:40.707Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuhcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.htensorrt_llm/_torch/modules/fused_moe/routing.pycpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-14T23:23:27.449Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.htensorrt_llm/_torch/modules/fused_moe/routing.pycpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-20T06:56:02.889Z
Learnt from: eopXD
Repo: NVIDIA/TensorRT-LLM PR: 6768
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:577-579
Timestamp: 2025-08-20T06:56:02.889Z
Learning: In cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, maxSequenceLength is now enforced as a non-optional argument in the BlockManager constructor, so concerns about std::nullopt defaulting to 0 are not applicable. When windowSize > maxSequenceLength, a warning should be added instead of handling optional parameter cases.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.hcpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-20T07:43:36.447Z
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.
Applied to files:
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuhcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/kernels/noAuxTcKernels.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.
Applied to files:
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-14T21:04:50.248Z
Learnt from: thorjohnsen
Repo: NVIDIA/TensorRT-LLM PR: 6910
File: cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp:0-0
Timestamp: 2025-08-14T21:04:50.248Z
Learning: In KV cache onboarding logic during prefill in cpp/tensorrt_llm/batch_manager/kvCacheManager.cpp, when calculating which blocks fall within the attention window, use getTokensPerBlock() to advance token indices rather than block->getUniqueTokens().size(), because the calculation needs to consider the post-prefill state where blocks will be filled to capacity, not their current token count.
Applied to files:
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cppcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu
📚 Learning: 2025-09-23T14:58:05.372Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/config.cu:42-49
Timestamp: 2025-09-23T14:58:05.372Z
Learning: In TensorRT-LLM NCCL device kernels (cpp/tensorrt_llm/kernels/nccl_device/), the token partitioning intentionally uses ceil-like distribution (same token_per_rank for all ranks) to ensure all ranks launch the same number of blocks. This is required for optimal NCCL device API barrier performance, even though it may launch extra blocks for non-existent tokens on later ranks. Runtime bounds checking in the kernel (blockID validation) handles the overshoot cases.
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cucpp/tensorrt_llm/kernels/noAuxTcKernels.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-08-21T02:39:12.009Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1475-1480
Timestamp: 2025-08-21T02:39:12.009Z
Learning: The min latency mode functionality in TensorRT-LLM MOE kernels (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu) is deprecated and no longer being maintained/updated, as confirmed by djns99. Bug reports and optimization suggestions for the computeStridesTmaWarpSpecializedLowLatencyKernel and related min latency code paths should be deprioritized.
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cucpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.hcpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Applied to files:
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cppcpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-11-14T11:22:03.729Z
Learnt from: nzmora-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 9163
File: tensorrt_llm/_torch/auto_deploy/custom_ops/quant.py:107-113
Timestamp: 2025-11-14T11:22:03.729Z
Learning: In TensorRT-LLM AutoDeploy custom ops, when adding hardware capability checks to select between kernel implementations (e.g., cuBLAS vs. CUDA kernel), use descriptive variable names that identify the specific GPU architectures or families being targeted (e.g., `is_blackwell_geforce_or_ada`) rather than generic names like `enable_cuda_core`. This makes it clear that the code is selecting an implementation path based on hardware capabilities, not enabling/disabling hardware features.
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/routing.pycpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-08T04:10:19.038Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6728
File: cpp/tensorrt_llm/plugins/mixtureOfExperts/mixtureOfExpertsPlugin.cpp:966-966
Timestamp: 2025-08-08T04:10:19.038Z
Learning: TensorRT plugins currently don't support padding functionality, and TensorRT is not getting new features (in maintenance mode). This means that duplicating parameters like mExpertHiddenSize in function calls, even with TODO comments, can be acceptable as pragmatic solutions within these constraints.
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
Applied to files:
cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-26T06:07:02.166Z
Learnt from: shaharmor98
Repo: NVIDIA/TensorRT-LLM PR: 7231
File: tensorrt_llm/_torch/pyexecutor/_util.py:504-509
Timestamp: 2025-08-26T06:07:02.166Z
Learning: In tensorrt_llm/_torch/pyexecutor/_util.py, when calling model_engine.set_lora_model_config(), pass model_binding_config.mlp_hidden_size directly without multiplying by mapping.tp_size, as the mlp_hidden_size from get_bindings_model_config() is already the per-TP rank value needed for LoRA weight packaging.
Applied to files:
cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp
📚 Learning: 2025-08-25T00:03:39.294Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1185-1189
Timestamp: 2025-08-25T00:03:39.294Z
Learning: TLLM_CHECK_WITH_INFO is a host-side utility function and cannot be called from CUDA device functions (those marked with __device__ or __global__). In device code, assert() is the primary mechanism for handling "should never happen" conditions, and like standard C++ assert, CUDA's assert only works in debug builds and is compiled out in release builds.
Applied to files:
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu
🧬 Code graph analysis (8)
cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
n_group(276-276)
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
n_group(276-276)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu (4)
cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (2)
topK(416-417)topK(502-503)cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)
topK(332-333)cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (2)
topK(496-498)topK(588-590)cpp/tests/unit_tests/kernels/routing/routingTest.h (1)
topK(231-231)
tensorrt_llm/_torch/modules/fused_moe/routing.py (2)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (2)
num_experts(269-269)top_k(275-275)tensorrt_llm/functional.py (1)
where(3043-3099)
cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (1)
n_group(276-276)
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (2)
cpp/tests/unit_tests/kernels/routing/routingRenormalizeTest.cpp (6)
param(39-150)param(39-39)param(152-158)param(152-152)param(190-196)param(190-191)cpp/tests/unit_tests/kernels/routing/routingLlama4Test.cpp (6)
param(39-91)param(39-39)param(93-99)param(93-93)param(120-126)param(120-121)
tests/unittest/_torch/thop/serial/test_moe.py (1)
tensorrt_llm/_torch/modules/fused_moe/routing.py (2)
RoutingMethodType(147-159)top_k(362-363)
cpp/tensorrt_llm/kernels/noAuxTcKernels.cu (3)
cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (2)
x(42-45)x(42-42)cpp/tests/unit_tests/kernels/routing/routingTest.h (1)
topkGroup(256-256)cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.h (2)
n_group(276-276)topk_group(278-278)
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🔇 Additional comments (29)
cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp (1)
105-118: Condition change looks correct.Changing from
n_group.value() != 0ton_group.value() > 1is semantically appropriate: whenn_group == 1, all experts belong to a single group, making group-based routing checks unnecessary. This aligns with the defaultn_group{0}inrunner.h:275which also indicates "no grouping."cpp/tensorrt_llm/thop/fp4BlockScaleMoe.cpp (1)
107-120: LGTM!The condition change is consistent with the other MoE files in this PR and correctly gates group-based routing checks to only apply when
n_group > 1.cpp/tensorrt_llm/thop/mxFp4BlockScaleMoe.cpp (1)
115-128: LGTM!The condition change correctly gates the group-based routing validation to only apply when there are multiple groups (
n_group > 1).cpp/tensorrt_llm/thop/fp8PerTensorScaleMoe.cpp (1)
108-121: LGTM!The condition change is consistent with the other MoE files in this PR and correctly restricts group-based routing validation to multi-group scenarios only.
tests/unittest/_torch/thop/parallel/test_noaux_tc.py (1)
8-14: New 512‑expert/top‑k test cases look consistent.The added
(512, 1, 1, 6)and(512, 1, 1, 22)combinations align with the new DeepSeek V3 single‑group routing support and exercise the extended kernel space without changing test logic.cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/DevKernel.h (1)
185-220: Macro extension for numTopExperts is wired through consistently.The extra
numTopExpertsparameter is plumbed through all dtype/flag branches ofLAUNCH_ROUTING_WITH_NUM_EXPERTS_FORCE_FLOAT_INPUTand intoLAUNCH_TILEN’s type pack, matching the newKernelParams<..., MaxNumTopExperts_, ...>template shape.cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernel.h (1)
192-235: KernelParams now exposes MaxNumTopExperts cleanly.Adding
MaxNumTopExperts_to the DeepSeekKernelParamstemplate and surfacing it asstatic constexpr int MaxNumTopExpertsaligns the struct with the updated launch macros and no‑aux top‑k kernels without affecting existing data wiring.cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu (1)
70-108: DeepSeek top‑k validation now matches kernel capacity.Relaxing the DeepSeek routing check from
topK <= 8totopK <= 22is consistent with the newMaxSupportedTopExpertsbound and the 512‑expert/22‑way specialization, while still guarding against unsupported larger values.tests/unittest/_torch/thop/serial/test_moe.py (1)
994-1066: FP4 MoE tests are ready for the 512‑expert/22‑way DeepSeek configuration.The new
RoutingDS_SuperV3entry (512 experts,top_k=22,n_groups=1) and the relaxedassert top_k <= 22inrun_moe_fp4_testline up with the extended DeepSeek routing kernels. Once the skip aroundtest_autotuneis removed, this will exercise the new Nemotron Super v3 path end‑to‑end.Would you like to also add a similar top‑k≤22 guard in any future FP8‑FP4 or per‑tensor FP8 tests if you plan to run 512/22 there as well, to keep test helpers consistent?
Also applies to: 1253-1255
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingKernelTopK.cuh (1)
36-39: MaxSupportedTopExperts constant correctly reflects the new 22‑way cap.Renaming the top‑k bound to
MaxSupportedTopExpertsand raising it to 22 keeps this header in sync with the updated routing kernels and runner checks for extended DeepSeek configurations.cpp/tests/unit_tests/kernels/routing/routingDeepSeekTest.cpp (3)
247-256: LGTM! New 512-expert test for cluster-level parallelization.The test parameters are consistent with the existing patterns for non-grouped tests (like
ClusterLevelParallelization384), and topK=22 aligns with the newMaxSupportedTopExpertsconstant.
324-333: LGTM! New 512-expert test for cooperative-level parallelization.Parameters follow the established cooperative-level test patterns with appropriate compute capability requirement.
357-366: LGTM! New 512-expert test for device-level parallelization.Test appropriately uses the score-based routing path (useTopKAsInput=false), consistent with the
DeviceLevelParallelization384test pattern.cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingDeepSeek.cu (11)
26-34: LGTM! Well-defined constants for Nemotron model support.The new constants clearly establish the 512-expert capacity and 22 top-K limit. Using
std::maxforMaxSupportedExpertCountis a clean approach that will automatically adapt if new expert counts are added.
130-131: LGTM! Arrays properly parameterized by template.Using
KernelParams::MaxNumTopExpertsfor array sizes allows different kernel instantiations to optimize for their specific top-K requirements.
168-171: LGTM! Proper bounds checking for limited groups.The additional conditions
(ii < params.mNumLimitedGroups) && (groupIdx < params.mNumExpertGroups)correctly prevent out-of-bounds access when fewer thanMaxNumTopGroupsgroups are in use.
182-209: LGTM! Correct handling of intermediate top-K storage.The shared memory sizing and indexing are correctly parameterized. The new initialization of unused slots (lines 204-208) with
invalidScoreFloatensures clean reduction whenmTopK < MaxNumTopExperts.
214-233: LGTM! Correct work distribution for final reduction.The
NumInterTopKPerThreadcalculation correctly determines how many intermediate results each lane processes during the final warp-level reduction.
305-306: LGTM! Template parameter correctly propagated.The
routingPermutationtemplate invocation correctly usesKernelParams::MaxNumTopExpertsfor consistency.
569-577: LGTM! Correctly extends expert count tiers.The new branch for
NumNemotronExperts(512) is correctly placed in ascending order after the 384-expert tier.
598-609: LGTM! Efficient top-K size selection for Nemotron.The conditional dispatch based on
mTopKallows using smaller arrays (DefaultMaxNumTopExperts=8) when top-K is small, avoiding unnecessary memory overhead when the full 22-element capacity isn't needed.
664-669: LGTM! Validation bounds correctly updated.The validation checks are appropriate:
numExperts >= MaxSupportedTopExpertsensures top-K can be supportednumExperts <= MaxSupportedExpertCountenforces the 512-expert limittopK <= MaxSupportedTopExpertsenforces the 22 top-K limit
695-700: LGTM! Thread count calculation handles both routing modes.The
max()correctly selects sufficient threads for either grouped routing (based on expert groups) or non-grouped routing (based on expert count).
688-692: The conditional placement of thenumExperts % 4check is correct and properly scoped.TensorRT-LLM uses two distinct kernel implementations: grouped routing uses optimized grouped GEMM kernels (when
numExpertGroups > 1), while non-grouped routing uses simpler per-expert/merged kernels (whennumExpertGroups == 1). The% 4divisibility constraint applies specifically to the grouped GEMM kernels' per-thread expert processing. Since non-grouped routing uses a different kernel family without this constraint, the conditional placement is appropriate.Likely an incorrect or invalid review comment.
cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/RoutingRenormalize.cu (5)
28-28: LGTM! Renamed constant for clarity.Renaming
MaxNumTopExpertstoMaxSupportedTopExpertsimproves clarity and aligns with the naming convention used inRoutingDeepSeek.cu. The value (10) remains appropriate for the renormalize routing path.
35-39: LGTM! Function signature clearly documents array bounds.The explicit
MaxSupportedTopExpertssizing in the function parameters makes the array size requirements clear to callers.
152-153: LGTM! Consistent naming throughout kernel functions.All top-K array declarations consistently use the renamed
MaxSupportedTopExpertsconstant.
359-365: LGTM! Template parameters correctly updated.Both
routingPermutationinvocations use the renamedMaxSupportedTopExpertstemplate parameter.
489-490: LGTM! Validation check uses renamed constant.The top-K validation correctly uses
MaxSupportedTopExpertswith an informative error message.
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Signed-off-by: Yue Weng <25103990+yweng0828@users.noreply.github.com> Added Top‑22 support for DeepSeek mode routing in the MoE TRTLLM‑GEN backend Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
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…nd trtllm moe backend (NVIDIA#9792) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
…nd trtllm moe backend (NVIDIA#9792) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
…ron (#2304) <!-- .github/pull_request_template.md --> ## 📌 Description - Support element wise activation (relu^2) in fused MoE in NVFP4 and in FP8PerTensor. - Use new `ActivationType` enum class instead of `GatedActType`. - Support Nemotron in deepseek routing as in NVIDIA/TensorRT-LLM#9792 - Remove 'A' suffix from `UseShuffledMatrixA` ## 🔍 Related Issues <!-- Link any related issues here --> ## 🚀 Pull Request Checklist Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete. ### ✅ Pre-commit Checks - [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method). - [x] I have installed the hooks with `pre-commit install`. - [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues. > If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/). ## 🧪 Tests - [ ] Tests have been added or updated as needed. - [ ] All tests are passing (`unittest`, etc.). ## Reviewer Notes <!-- Optional: anything you'd like reviewers to focus on, concerns, etc. --> <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **New Features** * Expanded activation options (Gelu, Relu, Silu, Swiglu, Geglu, SwigluBias, Relu2, Identity) and exposed ActivationType throughout the CLI and APIs. * DeepSeek routing supports larger top‑K and a configurable top‑experts dimension. * Added post‑GEMM element‑wise activation option and a CLI flag to select activation type. * **Breaking Changes** * ActivationType replaces the previous gated-activation enum in public APIs and tests; callers must use ActivationType values. <sub>✏️ Tip: You can customize this high-level summary in your review settings.</sub> <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
…ron, fixed (#2462) <!-- .github/pull_request_template.md --> ## 📌 Description - Support element wise activation (relu^2) in fused MoE in NVFP4 and in FP8PerTensor. - Use new ActivationType enum class instead of GatedActType. - Support Nemotron in deepseek routing as in NVIDIA/TensorRT-LLM#9792 - Remove 'A' suffix from UseShuffledMatrixA. NOTE: This is the fixed version of #2304 that was merged and reverted. - Replaced the problematic condition in deepseek routing that required `NumExperts >= MaxSupportedTopExperts` with `topK<=numExperts` - DeepSeek R1 works with it (tested with VLLM). - Removed irrelevant test cases. ## 🔍 Related Issues <!-- Link any related issues here --> ## 🚀 Pull Request Checklist Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete. ### ✅ Pre-commit Checks - [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method). - [x] I have installed the hooks with `pre-commit install`. - [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues. > If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/). ## 🧪 Tests - [ ] Tests have been added or updated as needed. - [ ] All tests are passing (`unittest`, etc.). ## Reviewer Notes <!-- Optional: anything you'd like reviewers to focus on, concerns, etc. --> <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **Refactor** * Replaced old gated-activation API with a unified ActivationType enum (many activation kinds supported). * Propagated activation_type across MoE workflows and kernels. * **New Features** * Added CLI option --activation-type to select activation kind for MoE benchmarks. * **Bug Fixes** * Enforced activation compatibility and validation for FP8/FP4 paths. * **Tests** * Updated and expanded tests to cover new activation types and compatibility scenarios. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
…ron, fixed (flashinfer-ai#2462) <!-- .github/pull_request_template.md --> ## 📌 Description - Support element wise activation (relu^2) in fused MoE in NVFP4 and in FP8PerTensor. - Use new ActivationType enum class instead of GatedActType. - Support Nemotron in deepseek routing as in NVIDIA/TensorRT-LLM#9792 - Remove 'A' suffix from UseShuffledMatrixA. NOTE: This is the fixed version of flashinfer-ai#2304 that was merged and reverted. - Replaced the problematic condition in deepseek routing that required `NumExperts >= MaxSupportedTopExperts` with `topK<=numExperts` - DeepSeek R1 works with it (tested with VLLM). - Removed irrelevant test cases. ## 🔍 Related Issues <!-- Link any related issues here --> ## 🚀 Pull Request Checklist Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete. ### ✅ Pre-commit Checks - [x] I have installed `pre-commit` by running `pip install pre-commit` (or used your preferred method). - [x] I have installed the hooks with `pre-commit install`. - [x] I have run the hooks manually with `pre-commit run --all-files` and fixed any reported issues. > If you are unsure about how to set up `pre-commit`, see [the pre-commit documentation](https://pre-commit.com/). ## 🧪 Tests - [ ] Tests have been added or updated as needed. - [ ] All tests are passing (`unittest`, etc.). ## Reviewer Notes <!-- Optional: anything you'd like reviewers to focus on, concerns, etc. --> <!-- This is an auto-generated comment: release notes by coderabbit.ai --> ## Summary by CodeRabbit * **Refactor** * Replaced old gated-activation API with a unified ActivationType enum (many activation kinds supported). * Propagated activation_type across MoE workflows and kernels. * **New Features** * Added CLI option --activation-type to select activation kind for MoE benchmarks. * **Bug Fixes** * Enforced activation compatibility and validation for FP8/FP4 paths. * **Tests** * Updated and expanded tests to cover new activation types and compatibility scenarios. <!-- end of auto-generated comment: release notes by coderabbit.ai --> --------- Signed-off-by: amitz-nv <203509407+amitz-nv@users.noreply.github.com>
Summary by CodeRabbit
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✏️ Tip: You can customize this high-level summary in your review settings.
Description
Add routing support for the new model for both cutlass and trtllm moe backend
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Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
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run [--reuse-test (optional)pipeline-id --disable-fail-fast --skip-test --stage-list "A10-PyTorch-1, xxx" --gpu-type "A30, H100_PCIe" --test-backend "pytorch, cpp" --add-multi-gpu-test --only-multi-gpu-test --disable-multi-gpu-test --post-merge --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx" --detailed-log --debug(experimental)]Launch build/test pipelines. All previously running jobs will be killed.
--reuse-test (optional)pipeline-id(OPTIONAL) : Allow the new pipeline to reuse build artifacts and skip successful test stages from a specified pipeline or the last pipeline if no pipeline-id is indicated. If the Git commit ID has changed, this option will be always ignored. The DEFAULT behavior of the bot is to reuse build artifacts and successful test results from the last pipeline.--disable-reuse-test(OPTIONAL) : Explicitly prevent the pipeline from reusing build artifacts and skipping successful test stages from a previous pipeline. Ensure that all builds and tests are run regardless of previous successes.--disable-fail-fast(OPTIONAL) : Disable fail fast on build/tests/infra failures.--skip-test(OPTIONAL) : Skip all test stages, but still run build stages, package stages and sanity check stages. Note: Does NOT update GitHub check status.--stage-list "A10-PyTorch-1, xxx"(OPTIONAL) : Only run the specified test stages. Examples: "A10-PyTorch-1, xxx". Note: Does NOT update GitHub check status.--gpu-type "A30, H100_PCIe"(OPTIONAL) : Only run the test stages on the specified GPU types. Examples: "A30, H100_PCIe". Note: Does NOT update GitHub check status.--test-backend "pytorch, cpp"(OPTIONAL) : Skip test stages which don't match the specified backends. Only support [pytorch, cpp, tensorrt, triton]. Examples: "pytorch, cpp" (does not run test stages with tensorrt or triton backend). Note: Does NOT update GitHub pipeline status.--only-multi-gpu-test(OPTIONAL) : Only run the multi-GPU tests. Note: Does NOT update GitHub check status.--disable-multi-gpu-test(OPTIONAL) : Disable the multi-GPU tests. Note: Does NOT update GitHub check status.--add-multi-gpu-test(OPTIONAL) : Force run the multi-GPU tests in addition to running L0 pre-merge pipeline.--post-merge(OPTIONAL) : Run the L0 post-merge pipeline instead of the ordinary L0 pre-merge pipeline.--extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx"(OPTIONAL) : Run the ordinary L0 pre-merge pipeline and specified test stages. Examples: --extra-stage "H100_PCIe-TensorRT-Post-Merge-1, xxx".--detailed-log(OPTIONAL) : Enable flushing out all logs to the Jenkins console. This will significantly increase the log volume and may slow down the job.--debug(OPTIONAL) : Experimental feature. Enable access to the CI container for debugging purpose. Note: Specify exactly one stage in thestage-listparameter to access the appropriate container environment. Note: Does NOT update GitHub check status.For guidance on mapping tests to stage names, see
docs/source/reference/ci-overview.mdand the
scripts/test_to_stage_mapping.pyhelper.kill
killKill all running builds associated with pull request.
skip
skip --comment COMMENTSkip testing for latest commit on pull request.
--comment "Reason for skipping build/test"is required. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.reuse-pipeline
reuse-pipelineReuse a previous pipeline to validate current commit. This action will also kill all currently running builds associated with the pull request. IMPORTANT NOTE: This is dangerous since lack of user care and validation can cause top of tree to break.