[https://nvbugs/5537738][fix] Add fp8 post-quant allgather support to release 1.1 #8322
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📝 WalkthroughWalkthroughSimplifies post-quant allgather gating to depend on data parallelism, adds handling for DeepSeek FP8 block scales and W4A16 MXFP4 padding, propagates top-k metadata into MoE runners, and conditionally omits router outputs when post-quant allgather is enabled. A single test-waive entry was removed. Changes
Sequence Diagram(s)sequenceDiagram
autonumber
participant C as Caller
participant G as FusedMoeGen
participant R as Router
participant RT as MoE Runtime
participant DP as DataParallel
C->>G: forward(x, config, use_dp, parallel_size, quant_flags)
Note over G: run_post_quant_allgather = use_dp && parallel_size > 1
alt run_post_quant_allgather
G->>DP: post-quant AllGather(x)
Note right of G: omit router outputs (router_logits=None, routing_bias=None)
else no allgather
G->>R: compute router_logits, routing_bias (may produce topk_ids/weights)
Note right of G: pad x if W4A16 MXFP4 and required
end
G->>RT: invoke runner(x[, topk_ids, topk_weights][, router_logits, routing_bias])
RT-->>G: moe outputs
G-->>C: return hidden_state/results
Estimated code review effort🎯 4 (Complex) | ⏱️ ~60 minutes
Pre-merge checks and finishing touches❌ Failed checks (1 warning)
✅ Passed checks (2 passed)
✨ Finishing touches
🧪 Generate unit tests (beta)
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📝 WalkthroughWalkthroughRefactors fused MoE generation logic to standardize post-quant allgather based on data parallelism, expands handling for additional quantization modes (DeepSeek FP8, W4A16 MXFP4), propagates top-k metadata through finalization paths, adjusts routing parameter passing under allgather, and updates tests by un-skipping a DeepSeek FP8 blockscale case. Changes
Sequence Diagram(s)sequenceDiagram
autonumber
participant U as Caller
participant G as FusedMoEGen
participant R as Router
participant Q as Quantizer
participant AG as DP AllGather
participant MR as MoE Runner
U->>G: generate(x, config, topk_args?)
G->>Q: quantize(x) / prepare x_sf
alt run_post_quant_allgather (use_dp && parallel_size>1)
G->>AG: allgather(x[, x_sf])
note right of AG: Routing params set to None<br/>Finalize ops skipped
else
G->>R: compute routing (router_logits, routing_bias, topk_ids, topk_weights)
end
rect rgba(230,240,255,0.5)
note over G,MR: Quant mode branches
alt DeepSeek FP8 block scales
G->>MR: fp8_block_scale_moe_runner(..., router=None if allgather)
else NVFP4 / W4A8 MXFP4 FP8 / MXFP8
G->>MR: corresponding moe_runner(..., padding?, top-k propagated)
else W4A16 MXFP4
G->>MR: bf16_mxe2m1_block_scale_moe_runner(..., padding?, top-k)
end
end
MR-->>G: outputs (+ token_final_scales, token_selected_experts as applicable)
G-->>U: final tokens / states
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes Pre-merge checks and finishing touches❌ Failed checks (1 warning)
✅ Passed checks (2 passed)
✨ Finishing touches
🧪 Generate unit tests (beta)
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Actionable comments posted: 1
🧹 Nitpick comments (1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (1)
343-347: Simplify by removing no-op assignment.The
elsebranch at line 347 contains a no-op assignmentx = x. Since the padding was already applied before allgather (lines 243-244) whenrun_post_quant_allgatheris True, you can simplify this code.Apply this diff:
- if not run_post_quant_allgather: - pad_size = self.w3_w1_weight.shape[-1] * 2 - x.shape[-1] - x = torch.nn.functional.pad(x, (0, pad_size)) - else: - x = x + if not run_post_quant_allgather: + pad_size = self.w3_w1_weight.shape[-1] * 2 - x.shape[-1] + x = torch.nn.functional.pad(x, (0, pad_size))
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tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (2)
tensorrt_llm/_torch/modules/fused_moe/interface.py (2)
has_deepseek_fp8_block_scales(293-296)has_w4a16_mxfp4(317-320)tensorrt_llm/_torch/custom_ops/trtllm_gen_custom_ops.py (1)
bf16_mxe2m1_block_scale_moe_runner(1355-1434)
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🔇 Additional comments (6)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (6)
240-244: Verify that DeepSeek FP8 requires no pre-allgather quantization.The empty
passstatement forhas_deepseek_fp8_block_scalesindicates that no quantization is performed before allgather for this mode. The FP8 quantization occurs later at line 269. Confirm this is the intended behavior and that the inputxin bfloat16 format can be safely allgathered without prior quantization.
272-273: LGTM: Correct parameter passing for post-quant allgather mode.When
run_post_quant_allgatheris True, routing is performed beforehand (lines 211-212), so the runner receivesNoneforrouter_logitsandrouting_biasbut gets pre-computedtopk_weightsandtopk_ids. This correctly avoids duplicate routing computation.Also applies to: 290-291
332-333: LGTM: Consistent top-k metadata propagation.The addition of
topk_weightsandtopk_idsparameters ensures consistent handling of pre-computed routing information across all MoE runner calls when post-quant allgather is enabled.
352-353: LGTM: Consistent routing parameter handling.The conditional passing of routing parameters and top-k metadata follows the same pattern as other MoE runners, ensuring uniform behavior across all quantization modes.
Also applies to: 376-377
420-421: LGTM: Top-k metadata properly propagated.The addition of
token_final_scalesandtoken_selected_expertsparameters to the remaining MoE runner calls completes the consistent propagation of routing metadata across all quantization modes.Also applies to: 463-464
202-481: Overall assessment: Well-structured implementation of FP8 post-quant allgather support.The changes systematically enable post-quant allgather for DeepSeek FP8 block scales and other quantization modes by:
- Simplifying the allgather condition (line 202) to apply universally when data parallelism is enabled
- Adding quantization-specific branches (lines 240-244) to handle different modes appropriately before allgather
- Propagating pre-computed routing metadata (topk_weights/topk_ids) throughout all MoE runner calls
- Conditionally bypassing redundant routing by passing None for router_logits/routing_bias when routing was already performed
The implementation is consistent across all five quantization modes (DeepSeek FP8, NVFP4, W4A16 MXFP4, W4A8 MXFP4 FP8, W4A8 MXFP4 MXFP8), ensuring uniform behavior. The changes align with the PR objective to fix the FP8 post-quant allgather bug for MoE.
Minor suggestions:
- Remove the no-op assignment at line 347 (addressed in separate comment)
- Verify the simplified allgather logic works correctly for all modes (verification script provided)
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Actionable comments posted: 0
♻️ Duplicate comments (1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (1)
240-248: Correct handling for DeepSeek FP8 and W4A16 MXFP4 modes in post-quant allgather.The
passforhas_deepseek_fp8_block_scalesis intentional—bf16 data is allgathered first, then quantized viafp8_quantize_1x128at line 269. The padding forhas_w4a16_mxfp4ensures proper tensor alignment before the allgather. This completes the coverage for all five quantization modes in the if-elif chain, addressing the concern from the previous review.
🧹 Nitpick comments (1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (1)
343-348: Minor: redundant assignmentx = x.Line 347 is a no-op since padding was already applied at lines 243-244 when
run_post_quant_allgatheris true. The logic is correct, but the else branch could be omitted entirely.if not run_post_quant_allgather: pad_size = self.w3_w1_weight.shape[-1] * 2 - x.shape[-1] x = torch.nn.functional.pad(x, (0, pad_size)) - else: - x = x + # else: padding was already applied in the run_post_quant_allgather block
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🧠 Learnings (11)
📓 Common learnings
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device allreduce implementation (cpp/tensorrt_llm/thop/allreduceOp.cpp), the goto pattern in runNCCLAllReduceDeviceFusion is intentionally used for future extensibility, allowing multiple switch cases to fallback to the default handler. While not aesthetically ideal, this pattern supports adding more fusion cases later that can reuse the same fallback logic.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-08T22:03:40.707Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1198-1209
Timestamp: 2025-08-08T22:03:40.707Z
Learning: In the CUTLASS MoE kernels (cpp/tensorrt_llm/cutlass_extensions), when `layout_info.fusion` is set to `TmaWarpSpecializedGroupedGemmInput::EpilogueFusion::FINALIZE`, the `router_scales` parameter must be non-null by design. The fused finalize kernel epilogue does not perform nullptr checks and requires valid router scales to function correctly. This is an implicit contract that callers must satisfy when enabling the FINALIZE fusion mode.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-14T23:23:27.449Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-09T20:57:04.084Z
Learnt from: sklevtsov-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 3294
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu:118-127
Timestamp: 2025-08-09T20:57:04.084Z
Learning: In the CUTLASS MoE finalize fusion implementation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_gemm_tma_warp_specialized_input.cu), when setting `fused_finalize_epilogue.stride_final_output` with shape `(hidden_size, num_output_tokens, 1)`, the `num_rows_in_final_output` should be set to `num_output_tokens` (not `hidden_size`) because of a swap+transpose operation that maps rows of the output tensor to `hidden_size` and columns to `num_output_tokens`.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-10-20T17:07:18.745Z
Learnt from: nvchenghaoz
Repo: NVIDIA/TensorRT-LLM PR: 8469
File: tensorrt_llm/_torch/auto_deploy/models/patches/nemotron_h.py:98-116
Timestamp: 2025-10-20T17:07:18.745Z
Learning: In NemotronH models (tensorrt_llm/_torch/auto_deploy/models/patches/nemotron_h.py), the gate (self.gate) returns topk_indices and topk_weights that are already in the correct shape to be passed directly to torch_ops.auto_deploy.torch_moe without needing to reshape them when hidden_states is flattened.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-21T02:39:12.009Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 7104
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:1475-1480
Timestamp: 2025-08-21T02:39:12.009Z
Learning: The min latency mode functionality in TensorRT-LLM MOE kernels (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu) is deprecated and no longer being maintained/updated, as confirmed by djns99. Bug reports and optimization suggestions for the computeStridesTmaWarpSpecializedLowLatencyKernel and related min latency code paths should be deprioritized.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-19T03:35:20.866Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4616-4626
Timestamp: 2025-08-19T03:35:20.866Z
Learning: In the MOE profiler TMA workspace preparation (cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu), the overlapping of TMA WS regions for NONE and FINALIZE variants is deliberate design to save memory space, as confirmed by djns99. The comment "reuse the same pointers to save space" reflects this intentional behavior.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
📚 Learning: 2025-08-14T06:36:40.701Z
Learnt from: timlee0212
Repo: NVIDIA/TensorRT-LLM PR: 6886
File: tensorrt_llm/_torch/models/modeling_deepseekv3.py:0-0
Timestamp: 2025-08-14T06:36:40.701Z
Learning: In DeepSeek V3 model (tensorrt_llm/_torch/models/modeling_deepseekv3.py), the disagreement between AllReduce.__init__ guard and _compute_mlp_tp_size logic for MNNVL usage is expected by design. The AllReduce component and MLP TP-size computation intentionally use different criteria for MNNVL availability decisions.
Applied to files:
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py
🧬 Code graph analysis (1)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (2)
tensorrt_llm/_torch/modules/fused_moe/interface.py (2)
has_deepseek_fp8_block_scales(293-296)has_w4a16_mxfp4(317-320)tensorrt_llm/_torch/custom_ops/trtllm_gen_custom_ops.py (1)
bf16_mxe2m1_block_scale_moe_runner(1355-1434)
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🔇 Additional comments (4)
tensorrt_llm/_torch/modules/fused_moe/fused_moe_trtllm_gen.py (4)
202-202: Simplified gating logic for post-quant allgather looks correct.The condition now correctly enables post-quant allgather for all quantization modes when data parallelism is active (
use_dp) and multiple ranks are involved (parallel_size > 1). The subsequent if-elif chain (lines 217-248) properly handles each quantization mode.
271-292: FP8 block scale MoE runner correctly receives pre-computed routing metadata.When
run_post_quant_allgatheris enabled, routing has already been computed (lines 211-215). Passingrouter_logits=Noneandrouting_bias=Nonewhile providingtopk_weightsandtopk_idsallows the runner to skip redundant routing computation and use the pre-gathered routing results. This is the key fix for the FP8 post-quant allgather support.
332-334: LGTM!The
topk_idsparameter is now correctly passed to the nvfp4 runner, completing the routing metadata propagation for this quantization path.
351-378: LGTM!The
bf16_mxe2m1_block_scale_moe_runnercall correctly handles the post-quant allgather scenario by conditionally passingNonefor routing inputs and propagating the pre-computedtoken_final_scalesandtoken_selected_expertsas the final positional arguments.
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… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
… release 1.1 (NVIDIA#8322) Signed-off-by: Christina Zhang <83400082+ChristinaZ@users.noreply.github.com> Signed-off-by: Mike Iovine <6158008+mikeiovine@users.noreply.github.com> Signed-off-by: Mike Iovine <miovine@nvidia.com>
3 participants
Description
Fix the bug related to the FP8 post-quant allgather for MoE TRTLLM backend (https://nvbugs/5537738)
Merge this commit to the release 1.1
Test Coverage
pytest -s -o log_cli=true "tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestDeepSeekR1::test_fp8_blockscale[throughput_mtp_trtllm]"
PR Checklist
Please review the following before submitting your PR:
PR description clearly explains what and why. If using CodeRabbit's summary, please make sure it makes sense.
PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
Test cases are provided for new code paths (see test instructions)
Any new dependencies have been scanned for license and vulnerabilities
CODEOWNERS updated if ownership changes
Documentation updated as needed
The reviewers assigned automatically/manually are appropriate for the PR.
Please check this after reviewing the above items as appropriate for this PR.
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Summary by CodeRabbit
New Features
Bug Fixes
Tests
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