[None][fix] xqa precision for fp16/bf16 kv cache #6573

Bruce-Lee-LY · 2025-08-03T03:49:42Z

Description

When the group size of the attention head in the xqa sm90 operator exceeds 8, errors will occur in the fp16/bf16 kv cache results.
Modifying the logic of the stmatrix part can fix this bug.

Summary by CodeRabbit

Refactor
- Enhanced internal data handling for better memory organization, with no impact on user-facing features or functionality.

coderabbitai · 2025-08-03T03:49:51Z

📝 Walkthrough

Walkthrough

A single change was made to the indexing logic within the saveTransposedOutput function template in cpp/kernels/xqa/mha_sm90.cu. The row index for accessing the shared memory buffer was modified from idxRow to 8 * n + idxRow, altering how output data is stored in shared memory. No other logic or public interface was affected.

Changes

Cohort / File(s)	Change Summary
Shared Memory Output Indexing Update `cpp/kernels/xqa/mha_sm90.cu`	Modified the row index calculation in `saveTransposedOutput` for the `SWAP_AB` specialization, changing the destination buffer access from `idxRow` to `8 * n + idxRow`. No other logic or interface changes.

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cpp/kernels/xqa/mha_sm90.cu (1 hunks)

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cpp/kernels/xqa/mha_sm90.cu

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coderabbitai

Actionable comments posted: 0

🧹 Nitpick comments (1)

cpp/kernels/xqa/mha_sm90.cu (1)
2-2: Update copyright year to current year.

The copyright header shows 2024 but should be updated to 2025 to comply with the coding guidelines requirement for TensorRT-LLM source files to contain the current year.
- * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.

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Reviewing files that changed from the base of the PR and between 3f7abf8 and 2b1b14c.

📒 Files selected for processing (1)

cpp/kernels/xqa/mha_sm90.cu (1 hunks)

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**/*.{cpp,h,hpp,cc,cxx,cu,py}

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All TensorRT-LLM Open Source Software code should contain an NVIDIA copyright header that includes the current year. This includes .cpp, .h, .cu, .py, and any other source files which are compiled or interpreted.

Files:

cpp/kernels/xqa/mha_sm90.cu

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GitHub Check: Pre-commit Check

🔇 Additional comments (1)

cpp/kernels/xqa/mha_sm90.cu (1)

2737-2737: LGTM! Indexing fix addresses precision issue for larger group sizes.

The change from idxRow to 8 * n + idxRow correctly addresses the precision bug in fp16/bf16 kv cache when group size exceeds 8. This modification ensures proper stride calculation for shared memory access patterns, accounting for the group structure in the data layout.

Signed-off-by: Bruce-Lee-LY <[email protected]>

dongjiyingdjy · 2025-08-04T03:27:20Z

/bot run

tensorrt-cicd · 2025-08-04T03:32:19Z

PR_Github #13913 [ run ] triggered by Bot

tensorrt-cicd · 2025-08-04T06:18:21Z

PR_Github #13913 [ run ] completed with state SUCCESS
/LLM/main/L0_MergeRequest_PR pipeline #10476 completed with status: 'SUCCESS'

Signed-off-by: Bruce-Lee-LY <[email protected]> Co-authored-by: Bruce-Lee-LY <[email protected]> Signed-off-by: Lanyu Liao <[email protected]>

Signed-off-by: Bruce-Lee-LY <[email protected]> Co-authored-by: Bruce-Lee-LY <[email protected]>

coderabbitai bot reviewed Aug 3, 2025

View reviewed changes

Bruce-Lee-LY changed the title ~~fix: xqa precision for fp16/bf16 kv cache~~ [None][fix] xqa precision for fp16/bf16 kv cache Aug 3, 2025

[None][fix] xqa precision for fp16/bf16 kv cache

6e92059

Signed-off-by: Bruce-Lee-LY <[email protected]>

svc-trtllm-gh-bot added the Community want to contribute PRs initiated from Community label Aug 3, 2025

lowsfer approved these changes Aug 4, 2025

View reviewed changes

dongjiyingdjy merged commit 8c82ee2 into NVIDIA:main Aug 4, 2025
4 checks passed

jain-ria pushed a commit to jain-ria/TensorRT-LLM that referenced this pull request Aug 7, 2025

[fix] xqa precision for fp16/bf16 kv cache (NVIDIA#6573)

57676e3

Signed-off-by: Bruce-Lee-LY <[email protected]> Co-authored-by: Bruce-Lee-LY <[email protected]>

coderabbitai bot mentioned this pull request Aug 14, 2025

[#6507][fix] Fix precision issue due to KV layout mismatch for split/concat kernels #6917

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[None][fix] xqa precision for fp16/bf16 kv cache #6573

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