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Perceived#58
RichardScottOZ wants to merge 1 commit into
NVIDIA:release/0.5.0from
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@nv-guomingz nv-guomingz added the Doc <NV>TRTLLM's textual/illustrative materials: API refs, guides, tutorials. Improvement & clarity. label Jun 13, 2024
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@RichardScottOZ Thanks for your contribution to TRT-LLM.
We've fixed this typo internally.
Sorry for the late response.

longcheng-nv added a commit to longcheng-nv/TensorRT-LLM that referenced this pull request Sep 3, 2026
An in-window +inf drives the register-family hint-free bracket max to
+inf, so the bracket width GMAX-Tv is +inf and SC=rcp(+inf)=0 folds every
value into bin 0. The whole-bin emit then ranks by position and drops the
+inf from the top-k (DKG issue NVIDIA#58; oracle and degenerate hints fail
identically, so this is in the selection, not the hint). The sentinel
fallback did not help because its own width (SENT_HI-SENT_LO) also
overflows to +inf.

The collapse guard now rejects an infinite bracket width, and the register
kernel forces the count-crossing escape whenever the bracket is degenerate
(okc=0). The escape ranks the full row in key space independent of the
bracket, where fkey(+inf) is the maximum key, so +inf is selected. The
finite +/-3e38 and -inf paths are unchanged; NaN ordering stays
implementation-specific per the documented limitation.

Verified on B200 sm100: the issue repro (in-/out-of-window +inf across
N in {4K,16K,64K}, cr in {1,4}) passes, the -inf duplicate-index sweep
(3 seed-dependent configs) stays fixed, and the full
test_gvr_selfsampling_topk suite is 82 passed.

Signed-off-by: longcheng-nv <243710427+longcheng-nv@users.noreply.github.com>
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